公开(公告)号：US6025625A

公开(公告)日：2000-02-15

申请号：US258083

申请日：1999-02-25

申请人： Min-hwa Chi

发明人： Min-hwa Chi

IPC分类号： H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L29/42336 ,  H01L27/115 ,  H01L29/7885 ,  G11C2216/10

摘要： A single-poly EEPROM cell comprising an inverter and a capacitive coupling area. The inverter is formed by: a p-well formed in a substrate; a gate structure formed atop the p-well and being formed from a thin gate oxide layer underneath a conductive layer; an n-base formed adjacent to a first edge of the gate structure and within the p-well; a p+ structure formed within the n-base; and a n+ structure adjacent a second edge of the gate structure and within the p-well. The capacitive coupling area is formed from a second p-well formed in the substrate and a floating gate, the floating gate formed from the conductive layer and capacitively coupled to the second p-well.

摘要翻译： 包括反相器和电容耦合区域的单个多晶EEPROM单元。 逆变器由以下部分形成：在衬底中形成的p阱; 形成在p阱顶上并由导电层下面的薄栅极氧化层形成的栅极结构; 形成在栅极结构的第一边缘附近并在p阱内的n基底; 在n基中形成的p +结构; 以及邻近门结构的第二边缘并且在p阱内的n +结构。 电容耦合区域由形成在衬底中的第二p阱和浮置栅极形成，浮置栅极由导电层形成并电容耦合到第二p阱。

公开(公告)号：US5908311A

公开(公告)日：1999-06-01

申请号：US690203

申请日：1996-07-25

申请人： Min-hwa Chi ,  Chih-sieh Teng ,  Albert Bergemont

发明人： Min-hwa Chi ,  Chih-sieh Teng ,  Albert Bergemont

IPC分类号： H01L21/8247 ,  H01L27/105

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： A CMOS device that includes three-volt MOS transistor, five-volt MOS transistors, FLASH EPROM cells, poly resistors, and double-poly capacitors is formed in a single integrated CMOS process flow. The FLASH EPROM cells are formed as single-transistor memory cells that operate on low to very-low voltages.

摘要翻译： 在单个集成CMOS工艺流程中形成包括三伏MOS晶体管，五伏MOS晶体管，FLASH EPROM单元，多晶硅电阻和双重多晶硅电容器的CMOS器件。 FLASH EPROM单元形成为在低至非常低的电压下工作的单晶体管存储单元。

公开(公告)号：US5814856A

公开(公告)日：1998-09-29

申请号：US857156

申请日：1997-05-15

申请人： Albert Bergemont ,  Min-hwa Chi

发明人： Albert Bergemont ,  Min-hwa Chi

IPC分类号： H01L29/788 ,  H01L29/76

CPC分类号： H01L29/7881 ,  H01L2924/0002

摘要： A MOSFET structure that utilizes self-aligned polysilicon and/or buried diffusion lines for coupling capacitors, provides a threshold voltage V.sub.T that is tunable from the control gate from positive (enhancement) to negative (depletion) by applying V.sub.cc to the bias gate and carefully designing the coupling ratio of the control gate and the bias gate. This scheme provides multiple V.sub.T 's on-chip without process complexity.

摘要翻译： 利用自对准多晶硅和/或用于耦合电容器的掩埋扩散线的MOSFET结构通过将Vcc施加到偏置栅极并且仔细地提供阈值电压VT，其可以从控制栅极从正（增强）到负（耗尽）可调 设计控制栅极和偏置栅极的耦合比。 该方案提供了多个VT芯片，无需过程复杂性。

公开(公告)号：US5753954A

公开(公告)日：1998-05-19

申请号：US684410

申请日：1996-07-19

申请人： Min-hwa Chi ,  Albert Bergemont

发明人： Min-hwa Chi ,  Albert Bergemont

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L27/115 ,  H01L29/7881

摘要： A single-poly neuron transistor is formed by utilizing a series of doped substrate regions in lieu of the input gates that are conventionally used to form neuron transistors. With conventional neuron transistors, the input gates are isolated from the floating gate by a layer of interpoly dielectric. In the present invention, the series of doped substrate regions are isolated from the floating gate by a layer of gate oxide.

摘要翻译： 通过利用一系列掺杂的衬底区域代替通常用于形成神经元晶体管的输入门来形成单聚聚神经元晶体管。 使用传统的神经元晶体管，输入栅极通过一层多晶硅电介质与浮动栅极隔离。 在本发明中，通过栅极氧化物层将一系列掺杂衬底区域从浮置栅极隔离开来。