公开(公告)号：US5908311A

公开(公告)日：1999-06-01

申请号：US690203

申请日：1996-07-25

申请人： Min-hwa Chi ,  Chih-sieh Teng ,  Albert Bergemont

发明人： Min-hwa Chi ,  Chih-sieh Teng ,  Albert Bergemont

IPC分类号： H01L21/8247 ,  H01L27/105

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： A CMOS device that includes three-volt MOS transistor, five-volt MOS transistors, FLASH EPROM cells, poly resistors, and double-poly capacitors is formed in a single integrated CMOS process flow. The FLASH EPROM cells are formed as single-transistor memory cells that operate on low to very-low voltages.

摘要翻译： 在单个集成CMOS工艺流程中形成包括三伏MOS晶体管，五伏MOS晶体管，FLASH EPROM单元，多晶硅电阻和双重多晶硅电容器的CMOS器件。 FLASH EPROM单元形成为在低至非常低的电压下工作的单晶体管存储单元。

公开(公告)号：US5761126A

公开(公告)日：1998-06-02

申请号：US796616

申请日：1997-02-07

申请人： Min-hwa Chi ,  Chih Sieh Teng ,  Albert Bergemont

发明人： Min-hwa Chi ,  Chih Sieh Teng ,  Albert Bergemont

IPC分类号： G11C16/04 ,  H01L29/788 ,  G11C11/34

CPC分类号： G11C16/0408 ,  H01L29/7881 ,  G11C2216/10

摘要： The layout and the programming voltage of a single-poly EPROM cell are reduced by eliminating the n+ contact region which is conventionally utilized to place a positive voltage on the n-well of the cell, and by utilizing a negative voltage to program the cell. The negative voltage is applied to a p+ contact region formed in the n-well which injects electrons directly onto the floating gate of the cell.

摘要翻译： 通过消除通常用于在电池的n阱上放置正电压的n +接触区域，并且通过利用负电压来对电池进行编程来减小单聚EPROM单元的布局和编程电压。 负电压被施加到形成在n阱中的p +接触区域，其将电子直接注入到电池的浮动栅极上。

公开(公告)号：US06509606B1

公开(公告)日：2003-01-21

申请号：US09053199

申请日：1998-04-01

申请人： Richard B. Merrill ,  Albert Bergemont ,  Min-hwa Chi

发明人： Richard B. Merrill ,  Albert Bergemont ,  Min-hwa Chi

IPC分类号： H01L29788

CPC分类号： H01L29/7883 ,  G11C2216/10 ,  H01L27/115

摘要： Leakage of a single-poly EPROM cell is prevented by eliminating field oxide isolating the source, channel, and drain from the control gate n-well, and by replacing field oxide surrounding the cell with a heavily doped surface isolation region. The EPROM cell also utilizes a floating gate having an open-rectangular floating gate portion over the control gate region, and a narrow floating gate portion over the channel and intervening silicon substrate. The surface area of the open-rectangular floating gate portion ensures a high coupling ratio with the control gate region. The small width of the narrow floating gate portion prevents formation of a sizeable leakage path between the n-well and the source, channel, and drain. To conserve surface area, the EPROM cell also eliminates the p+ contact region and the PLDD region in the control gate well of the conventional EPROM design. This is permitted because the VTp implant step is masked, permitting the control gate region to operate in accumulation mode during application of 5V programming voltages.

摘要翻译： 通过消除从控制栅极n阱分离源极，沟道和漏极的场氧化物，并且通过用重掺杂的表面隔离区域代替围绕电池的场氧化物来防止单聚EPROM单元的泄漏。 EPROM单元还利用在控制栅极区域上具有开放矩形浮动栅极部分的浮动栅极，以及在沟道上方的窄浮动栅极部分和中间的硅衬底。 开放式矩形浮动栅极部分的表面积确保与控制栅极区域的高耦合率。 窄浮动栅极部分的小宽度防止在n阱和源极，沟道和漏极之间形成相当大的泄漏路径。 为了节省表面积，EPROM单元还消除了常规EPROM设计中控制栅极中的p +接触区域和PLDD区域。 这是允许的，因为VTp注入步骤被屏蔽，允许控制栅极区域在施加5V编程电压期间以累积模式工作。

公开(公告)号：US6011295A

公开(公告)日：2000-01-04

申请号：US898062

申请日：1997-07-22

申请人： Richard Billings Merrill ,  Albert Bergemont ,  Min-hwa Chi

发明人： Richard Billings Merrill ,  Albert Bergemont ,  Min-hwa Chi

IPC分类号： G06N3/063 ,  G06G7/16

CPC分类号： G06N3/0635

摘要： An active pixel image cell which includes a photosensor, active devices for control of the sensor and readout of a signal representing the intensity of light to which the sensor is exposed, and a neuron MOSFET transistor which "both amplifies the signal from the photosensor and" simulates the behavior of a human neuron. An integrated neural network and imaging array may be formed by interconnecting a group of such pixels. Digital signal processing algorithms used for image processing may be implemented at the pixel level by appropriate interconnections between the output signals from the photosensor of surrounding pixels and the neuron MOSFET.

摘要翻译： 包括光传感器的有源像素图像单元，用于控制传感器的有源器件和表示传感器所暴露的光的强度的信号的读出，以及“两者都放大来自光电传感器的信号”的神经元晶体管， 模拟人类神经元的行为。 可以通过将一组这样的像素互连来形成集成神经网络和成像阵列。 用于图像处理的数字信号处理算法可以通过来自周围像素的光电传感器的输出信号和神经元MOSFET之间的适当互连在像素级上实现。

公开(公告)号：US5566044A

公开(公告)日：1996-10-15

申请号：US438549

申请日：1995-05-10

申请人： Albert Bergemont ,  Carver A. Mead ,  Min-hwa Chi ,  Hosam Haggag

发明人： Albert Bergemont ,  Carver A. Mead ,  Min-hwa Chi ,  Hosam Haggag

IPC分类号： H01L27/146 ,  H01L31/11 ,  H01G4/06 ,  H01L23/58 ,  H01L31/062 ,  H01L31/18

CPC分类号： H01L31/1105 ,  H01L27/14681

摘要： A technique for decreasing the effective gain of a bipolar phototransistor at high light levels makes the image usable over a greatly extended range of illumination conditions. The effective current gain at high light levels is reduced by fabricating a "non-ideal" emitter, such as by inserting a thin 20 521 tunnel oxide between the emitter and base junction. The tunnel oxide between the emitter and base serves as a variable resistor as well as a good junction for carrier injection from the emitter. The total base voltage is the sum of the oxide voltage and the intrinsic base voltage. At high image intensity, the bipolar phototransistor will gradually enter into the saturation mode, i.e., the base to collector junction is forward biased. The beta is thus reduced. The bias of the collector should be about 0.3-0.8 V higher than the emitter at the 20.ANG. tunnel oxide thickness for optimum operation.

摘要翻译： 降低双极光电晶体管在高光照条件下的有效增益的技术使得图像在大范围的照明条件下可用。 通过制造“非理想”发射器，例如通过在发射极和基极结之间插入薄的20 521隧道氧化物，可以降低高光级的有效电流增益。 发射极和基极之间的隧道氧化物用作可变电阻器，以及用于从发射极注入载流子的良好结。 总基极电压是氧化物电压和本征基极电压之和。 在高图像强度下，双极光电晶体管将逐渐进入饱和模式，即基极到集电极结正向偏置。 因此，beta被减少了。 在20 ANGSTROM隧道氧化物厚度下，集电极的偏压应比发射极高0.3-0.8V，以获得最佳的操作。

公开(公告)号：US5856222A

公开(公告)日：1999-01-05

申请号：US851252

申请日：1997-05-05

申请人： Albert Bergemont ,  Min-hwa Chi

发明人： Albert Bergemont ,  Min-hwa Chi

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： A method of fabricating an EEPROM cell structure in a semiconductor substrate includes forming a layer of silicon oxide having a first thickness on the silicon substrate. N-type dopant is then introduced into the semiconductor substrate to define a buried region beneath the silicon oxide layer. Next, a tunnel window opening is formed in the silicon oxide layer to expose a surface area of the buried region. A layer of tunnel oxide is then grown in the tunnel window opening on the exposed surface of the buried region, such that the tunnel oxide has a thickness that is less than the thickness of the silicon oxide. A first layer of polysilicon is then formed on the structure resulting from the foregoing steps, followed by an overlaying layer of oxide.backslash.nitride.backslash.oxide (ONO) and an overlying layer of second polysilicon. The poly-2, ONO.backslash.poly-1 sandwich is then anisotropically etched to form first and second stacks which provide the floating gate/control gate electrodes for the EEPROM cell access transistor and the EEPROM cell storage cell structure, respectively.

摘要翻译： 在半导体衬底中制造EEPROM单元结构的方法包括在硅衬底上形成具有第一厚度的氧化硅层。 然后将N型掺杂剂引入半导体衬底中以限定氧化硅层下面的掩埋区域。 接下来，在氧化硅层中形成隧道窗口以露出掩埋区域的表面区域。 然后在掩埋区域的暴露表面上的隧道窗口中生长隧道氧化物层，使得隧道氧化物的厚度小于氧化硅的厚度。 然后在由上述步骤产生的结构上形成第一层多晶硅，随后是氧化物+ 544氮化物+ 544氧化物（ONO）的覆盖层和第二多晶硅的上覆层。 然后各向异性地蚀刻poly-2，ONO + 544 poly-1夹层以形成分别为EEPROM单元存取晶体管和EEPROM单元存储单元结构提供浮置栅极/控制栅电极的第一和第二堆叠。

公开(公告)号：US5587949A

公开(公告)日：1996-12-24

申请号：US429644

申请日：1995-04-27

申请人： Albert Bergemont ,  Min-hwa Chi

发明人： Albert Bergemont ,  Min-hwa Chi

IPC分类号： G11C11/56 ,  G11C16/10 ,  G11C13/00

CPC分类号： G11C16/10 ,  G11C11/5621 ,  G11C11/5628

摘要： Multiple logic levels can be simultaneously programmed into any combination of memory cells in a column of an ETOX array by applying one of a corresponding number of programming voltages to the word lines that correspond with the cells to be programmed. In the present invention, the memory cells in the array form a punchthrough current during programming which, in turn, leads to the formation of an increased number of substrate hot electrons. By utilizing the substrate hot electrons formed from the punchthrough current in addition to the channel hot electrons, much lower control gate voltages can be utilized during programming.

摘要翻译： 通过将相应数量的编程电压中的一个应用于与要编程的单元相对应的字线，可以将多个逻辑电平同时编程到ETOX阵列列中的存储单元的任何组合。 在本发明中，阵列中的存储单元在编程期间形成穿透电流，这又导致形成更多数量的衬底热电子。 除了沟道热电子之外，通过利用由穿通电流形成的衬底热电子，在编程期间可以利用更低的控制栅极电压。

公开(公告)号：US5557567A

公开(公告)日：1996-09-17

申请号：US417938

申请日：1995-04-06

申请人： Albert Bergemont ,  Min-hwa Chi

发明人： Albert Bergemont ,  Min-hwa Chi

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C11/34

CPC分类号： G11C16/0491 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C2211/5622

摘要： Multiple logic levels can be simultaneously programmed into any combination of memory cells in a column of an alternate-metal virtual-ground (AMG) EPROM or flash memory array by applying one of a corresponding number of programming voltages to the word lines that correspond with the cells to be programmed. In the present invention, the memory cells in the array form a punchthrough current during programming which, in turn, leads to the formation of an increased number of substrate hot electrons. By utilizing the substrate hot electrons formed from the punchthrough current in addition to the channel hot electrons, much lower control gate voltages can be utilized during programming.

摘要翻译： 可以将多个逻辑电平同时编程到备用金属虚拟地（AMG）EPROM或闪存阵列的列中的存储器单元的任意组合中，通过将相应数量的编程电压中的一个应用于与 要编程的单元格。 在本发明中，阵列中的存储单元在编程期间形成穿透电流，这又导致形成更多数量的衬底热电子。 除了沟道热电子之外，通过利用由穿通电流形成的衬底热电子，在编程期间可以利用更低的控制栅极电压。

公开(公告)号：US6008508A

公开(公告)日：1999-12-28

申请号：US713026

申请日：1996-09-12

申请人： Albert Bergemont ,  Min-hwa Chi

发明人： Albert Bergemont ,  Min-hwa Chi

IPC分类号： H01L27/02 ,  H01L29/06

CPC分类号： H01L27/0262 ,  H01L2924/0002

摘要： Disclosed is a floating gate neuron MOS transistor that may be incorporated into devices such as low voltage silicon control rectifiers for protection of internal circuits against electrostatic discharge. The transistor includes two or more input gates capacitively coupled to the floating gate. By adjusting the coupling ratio of the input gates, it is possible to control the transistor drain turn-on voltage very precisely and thereby turn on the rectifier without relying on avalanche breakdown of the transistor.

摘要翻译： 公开了一种浮栅神经元MOS晶体管，其可以并入诸如用于保护内部电路免受静电放电的低压硅控制整流器的器件中。 晶体管包括电容耦合到浮置栅极的两个或更多个输入栅极。 通过调整输入栅极的耦合比，可以非常精确地控制晶体管漏极导通电压，从而导通整流器，而不依赖于晶体管的雪崩击穿。

公开(公告)号：US5962844A

公开(公告)日：1999-10-05

申请号：US923370

申请日：1997-09-03

申请人： Richard Billings Merrill ,  Albert Bergemont ,  Min-hwa Chi

发明人： Richard Billings Merrill ,  Albert Bergemont ,  Min-hwa Chi

IPC分类号： H01L27/146 ,  H04N5/3745 ,  H04N5/378 ,  H01L27/148 ,  H04N5/335

CPC分类号： H04N3/155 ,  H01L27/14609

摘要： An active pixel image cell which includes a photosensor and an embedded memory element and may be used to produce signals corresponding to the photosensor outputs for successive frames. The structure of the active pixel cell includes an analog, non-volatile, or dynamic memory element and the control elements needed to store the output of the photosensor generated during a previous frame. The pixel elements then generate a signal representing the current frame output of the photosensor. The current frame output and previous frame output are then provided as output signals for the pixel and may be subjected to off-pixel processing as desired. For example, the two values may be subtracted from one another by an off-pixel difference amplifier to form a signal representing the difference between the image on the photodiode sensor of the pixel between successive frames. The difference signal may then be used for purposes of video compression, motion detection, or image stabilization.

摘要翻译： 一种有源像素图像单元，其包括光电传感器和嵌入式存储元件，并且可用于产生对应于用于连续帧的光电传感器输出的信号。 有源像素单元的结构包括模拟，非易失性或动态存储器元件以及存储在先前帧期间产生的光电传感器的输出所需的控制元件。 然后，像素元件产生表示光电传感器的当前帧输出的信号。 然后将当前帧输出和先前帧输出提供为像素的输出信号，并且可以根据需要进行离像像素处理。 例如，两个值可以由离像素差分放大器彼此减去以形成表示连续帧之间的像素的光电二极管传感器上的图像之间的差的信号。 然后差分信号可以用于视频压缩，运动检测或图像稳定的目的。