Low-power predecoding based viterbi decoding
    51.
    发明授权
    Low-power predecoding based viterbi decoding 有权
    基于低功率预编码的维特比解码

    公开(公告)号:US08230313B2

    公开(公告)日:2012-07-24

    申请号:US12538631

    申请日:2009-08-10

    IPC分类号: H03M13/03 H03D1/00 H04L27/06

    摘要: In at least some disclosed embodiments, a system includes a Viterbi decoder and predecoding logic coupled to the Viterbi decoder. The predecoding logic decodes encoded data. The system further includes detection logic coupled to the predecoding logic. The detection logic tests decoded data, and the detection logic produces a binary result. The Viterbi decoder is enabled if the binary result is a first value, and the Viterbi decoder is disabled if the binary result is a second value.

    摘要翻译: 在至少一些公开的实施例中,系统包括维特比解码器和耦合到维特比解码器的预解码逻辑。 预解码逻辑解码编码数据。 该系统还包括耦合到预解码逻辑的检测逻辑。 检测逻辑测试解码数据,检测逻辑产生二进制结果。 如果二进制结果是第一个值,则维特比解码器被使能,如果二进制结果是第二个值,则维特比解码器被禁用。

    LOW-POWER PREDECODING BASED VITERBI DECODING
    52.
    发明申请
    LOW-POWER PREDECODING BASED VITERBI DECODING 有权
    基于低功耗预测的VITERBI解码

    公开(公告)号:US20100034325A1

    公开(公告)日:2010-02-11

    申请号:US12538631

    申请日:2009-08-10

    IPC分类号: H04L27/06 H03M13/03

    摘要: In at least some disclosed embodiments, a system includes a Viterbi decoder and predecoding logic coupled to the Viterbi decoder. The predecoding logic decodes encoded data. The system further includes detection logic coupled to the predecoding logic. The detection logic tests decoded data, and the detection logic produces a binary result. The Viterbi decoder is enabled if the binary result is a first value, and the Viterbi decoder is disabled if the binary result is a second value.

    摘要翻译: 在至少一些公开的实施例中,系统包括维特比解码器和耦合到维特比解码器的预解码逻辑。 预解码逻辑解码编码数据。 该系统还包括耦合到预解码逻辑的检测逻辑。 检测逻辑测试解码数据,检测逻辑产生二进制结果。 如果二进制结果是第一个值,则维特比解码器被使能,如果二进制结果是第二个值,则维特比解码器被禁用。

    Scalable gain training generator, method of gain training and MIMO communication system employing the generator and method
    53.
    发明授权
    Scalable gain training generator, method of gain training and MIMO communication system employing the generator and method 有权
    可扩展增益训练发生器,增益训练方法和采用发电机和方法的MIMO通信系统

    公开(公告)号:US07457369B2

    公开(公告)日:2008-11-25

    申请号:US11028829

    申请日:2005-01-04

    IPC分类号: H04B7/02

    CPC分类号: H04B7/0697

    摘要: The present invention provides a gain training generator for use with a multiple-input, multiple-output (MIMO) transmitter employing N transmit antennas where N is at least two. In one embodiment, the gain training generator includes a fundamental training encoder configured to provide a basic gain training sequence to one of the N transmit antennas during a time interval to produce a basic gain training waveform having a basic peak-to-average ratio (PAR). Additionally, the gain training generator also includes a supplemental training encoder coupled to the fundamental training encoder and configured to further provide (N−1) supplemental gain training sequences to (N−1) remaining transmit antennas, respectively, during the time interval to produce supplemental gain training waveforms wherein each has a supplemental PAR substantially equal to the basic PAR.

    摘要翻译: 本发明提供一种增益训练发生器,其用于与N个至少两个的N个发射天线的多输入多输出(MIMO)发射机一起使用。 在一个实施例中,增益训练发生器包括基本训练编码器,其被配置为在时间间隔期间向N个发射天线之一提供基本增益训练序列,以产生具有基本峰均比(PAR)的基本增益训练波形 )。 另外,增益训练发生器还包括耦合到基本训练编码器的辅助训练编码器,并且被配置为在产生时间间隔内分别向(N-1)个剩余发射天线提供(N-1)个补充增益训练序列 补充增益训练波形,其中每个具有基本上等于基本PAR的补充PAR。

    Scalable Data Reception Gain Control for a Multiple-Input, Multiple-Output (MIMO) Communications System
    54.
    发明申请
    Scalable Data Reception Gain Control for a Multiple-Input, Multiple-Output (MIMO) Communications System 审中-公开
    用于多输入多输出(MIMO)通信系统的可扩展数据接收增益控制

    公开(公告)号:US20080192869A1

    公开(公告)日:2008-08-14

    申请号:US12106548

    申请日:2008-04-21

    IPC分类号: H04L27/08

    摘要: The present invention provides a concurrent gain generator for use with a MIMO transmitter havi'ng an N of two or more transmit antennas. In one embodiment, the concurrent gain generator includes a first sequence formatter that provides one of the N transmit antennas with a gain training sequence during an initial time interval, and a second sequence formatter that further provides (N−1) remaining transmit antennas with (N−1) additional gain training sequences during the initial time interval to train receive gains. The present invention also provides a non-concurrent gain adjuster for use with a MIMO receiver employing an M of two or more receive antennas. In one embodiment, the non-concurrent gain adjuster includes a gain combiner that computes a common receive gain as a function of M independent receive gains, and a gain applier that applies the common receive gain to receivers associated with the M receive antennas.

    摘要翻译: 本发明提供一种并发增益发生器,用于与两个或更多发射天线的N个的MIMO发射机一起使用。 在一个实施例中,并发增益生成器包括第一序列格式化器,其在初始时间间隔期间向N个发送天线之一提供增益训练序列;以及第二序列格式器,其进一步向(N-1)个剩余的发射天线提供(N-1) N-1)在初始时间间隔期间训练接收增益的附加增益训练序列。 本发明还提供了一种与使用两个或更多个接收天线的M的MIMO接收机一起使用的非并发增益调整器。 在一个实施例中,非并发增益调整器包括增益组合器,该增益组合器计算作为M个独立接收增益的函数的公共接收增益;以及增益施加器,其将公共接收增益应用于与M个接收天线相关联的接收机。

    De-interleaver synchronization methods and apparatus
    55.
    发明申请
    De-interleaver synchronization methods and apparatus 审中-公开
    去交织器同步方法和装置

    公开(公告)号:US20070140292A1

    公开(公告)日:2007-06-21

    申请号:US11311447

    申请日:2005-12-17

    IPC分类号: H04J3/22

    摘要: A methods and apparatus for synchronizing a de-interleaver are disclosed. One example method includes fixing a phase of a de-interleaver in a first state; de-interleaving symbols in the signal while the phase of the de-interleaver is in the first state; processing the de-interleaved symbols; detecting if the known information is present in the processed de-interleaved symbols; and switching the phase of the de-interleaver between the first state and a second state when the known information is detected in the processed de-interleaved symbols.

    摘要翻译: 公开了一种用于同步解交织器的方法和装置。 一个示例性方法包括将解交织器的相位固定在第一状态; 在解交织器的相位处于第一状态时在信号中解交织符号; 处理解交织符号; 检测已知信息是否存在于经处理的去交织符号中; 以及当在已处理的解交织符号中检测到已知信息时,将解交织器的相位切换在第一状态和第二状态之间。

    Combined IFFT and FFT system
    56.
    发明申请
    Combined IFFT and FFT system 审中-公开
    组合IFFT和FFT系统

    公开(公告)号:US20060224651A1

    公开(公告)日:2006-10-05

    申请号:US11095275

    申请日:2005-03-31

    IPC分类号: G06F17/14

    CPC分类号: G06F17/142

    摘要: A system (12) for determining discrete transforms as between time and frequency domains. The system comprises a grid (60) comprising adders and multipliers. The grid is operable to perform in parallel an integer number P operations of a first transform function selected from one of either an IFFT or an FFT. The system also comprises the integer number of P serially-operating pipelines (641-648). Each of the pipelines is coupled to the grid and is operable to perform serially over a number of cycles an integer number S operations of the first transform. In the system, S and P are both greater than one and, in combination, the grid and the serially-operating pipelines perform the first transform type as an S×P-point transform. In a first instance at least a portion of the grid is operable to perform IFFT operations. In a second instance at least a portion of the grid is operable to perform FFT operations.

    摘要翻译: 一种用于确定时域和频域之间的离散变换的系统(12)。 该系统包括包括加法器和乘法器的格(60)。 网格可操作以并行执行从IFFT或FFT中的一个中选择的第一变换函数的整数P运算。 该系统还包括整数个P串行操作的管线(64×1〜64< 8>)。 每个管道耦合到电网并且可操作以串行地执行第一变换的整数S个操作的多个周期。 在系统中,S和P都大于1,并且组合在一起,网格和串行操作的管线执行第一变换类型作为SxP点变换。 在第一情况下,网格的至少一部分可操作以执行IFFT操作。 在第二种情况下,网格的至少一部分可操作以执行FFT操作。

    Methods and systems for a multi-channel fast fourier transform (FFT)
    57.
    发明申请
    Methods and systems for a multi-channel fast fourier transform (FFT) 有权
    用于多通道快速傅里叶变换(FFT)的方法和系统

    公开(公告)号:US20060167964A1

    公开(公告)日:2006-07-27

    申请号:US11336459

    申请日:2006-01-20

    IPC分类号: G06F17/14

    CPC分类号: H04L27/265 G06F17/142

    摘要: In at least some embodiments, a method is provided. The method includes receiving samples from a first input channel and a second input channel. The method further includes controlling commutators to selectively switch samples between the first and second input channels for input to a radix-2 butterfly. The method further includes continuously activating the radix-2 butterfly while processing samples received from the first input channel followed by samples received from the second input channel.

    摘要翻译: 在至少一些实施例中,提供了一种方法。 该方法包括从第一输入通道和第二输入通道接收采样。 该方法还包括控制换向器以选择性地在第一和第二输入通道之间切换采样,以输入到基数-2蝴蝶。 该方法还包括在处理从第一输入通道接收的样本后跟从第二输入通道接收的采样时连续激活基数-2蝶形。

    Collision avoidance manager, method of avoiding a memory collision and a turbo decoder employing the same
    58.
    发明申请
    Collision avoidance manager, method of avoiding a memory collision and a turbo decoder employing the same 审中-公开
    冲突避免管理器,避免存储器冲突的方法和采用该冲突的turbo解码器

    公开(公告)号:US20060083174A1

    公开(公告)日:2006-04-20

    申请号:US11239498

    申请日:2005-09-29

    IPC分类号: H04L12/26

    摘要: The present invention provides a collision avoidance manager for use with single-port memories. In one embodiment, the collision avoidance manager includes a memory structuring unit configured to provide a memory arrangement of the single-port memories having upper and lower memory banks arranged into half-memory portions. Additionally, the collision avoidance manager also includes a write memory alignment unit coupled to the memory structuring unit and configured to provide double-data writing to the memory arrangement based on memory collision avoidance. In a preferred embodiment, the collision avoidance manager also includes a read memory alignment unit coupled to the memory structuring unit and configured to provide double-data reading from the memory arrangement while maintaining the memory collision avoidance.

    摘要翻译: 本发明提供了一种与单端口存储器一起使用的防碰撞管理器。 在一个实施例中,冲突避免管理器包括存储器结构单元,其被配置为提供具有布置成半存储器部分的上部和下部存储器组的单个端口存储器的存储器布置。 此外,防撞管理器还包括耦合到存储器构造单元并被配置为基于存储器冲突避免向存储器装置提供双数据写入的写存储器对准单元。 在优选实施例中,防碰撞管理器还包括耦合到存储器结构单元并被配置为在保持存储器冲突避免的同时从存储器装置提供双数据读取的读取存储器对准单元。

    Scalable gain retraining generator, method of gain retraining and multiple-input, multiple-output communications system employing the generator or method
    59.
    发明申请
    Scalable gain retraining generator, method of gain retraining and multiple-input, multiple-output communications system employing the generator or method 审中-公开
    可扩展增益再培训发电机,增益再培训方法和多输入多输出通信系统采用发电机或方法

    公开(公告)号:US20060072681A1

    公开(公告)日:2006-04-06

    申请号:US10956406

    申请日:2004-10-01

    IPC分类号: H04B7/02

    CPC分类号: H04B7/0413

    摘要: The present invention provides a gain retraining generator for use with a MIMO transmitter employing N transmit antennas, where N is at least two. In one embodiment, the gain retraining generator includes a first sequence encoder configured to provide a gain retraining sequence to one of the N transmit antennas during a non-initial time interval. The gain retraining generator also includes a second sequence encoder coupled to the first sequence encoder and configured to further provide (N-1) alternative gain retraining sequences to (N-1) remaining transmit antennas, respectively, during the non-initial time interval to retrain receive gains for multiple concurrent data transmissions.

    摘要翻译: 本发明提供了一种与使用N个发射天线的MIMO发射机一起使用的增益再训练发生器,其中N是至少两个。 在一个实施例中,增益再培训发生器包括第一序列编码器,其被配置为在非初始时间间隔期间向N个发射天线之一提供增益再训练序列。 增益再培训发生器还包括耦合到第一序列编码器的第二序列编码器,并且被配置为在非初始时间间隔期间进一步向(N-1)个剩余发射天线提供(N-1)替代增益再训练序列, 重新训练接收多个并行数据传输的增益。

    Radix-N architecture for deinterleaver-depuncturer block
    60.
    发明授权
    Radix-N architecture for deinterleaver-depuncturer block 有权
    Radix-N架构用于解交织器 - 切除器块

    公开(公告)号:US06993702B2

    公开(公告)日:2006-01-31

    申请号:US10322875

    申请日:2002-12-18

    IPC分类号: H03M13/03

    摘要: A de-interleaver-de-puncturer architecture is scalable and capable of achieving a higher data throughput than that achievable using a conventional disjointed de-interleaver-de-puncturer architecture. The higher data throughput is achieved without increasing the clock speed of the de-interleaver. The scalable de-interleaver-de-puncturer architecture is also less complex than a conventional disjointed de-interleaver-de-puncturer architecture.

    摘要翻译: 去交织器去穿孔器架构是可扩展的并且能够实现比使用常规的不连续去交织器去穿孔器架构可实现的数据吞吐量更高的数据吞吐量。 在不增加解交织器的时钟速度的情况下实现较高的数据吞吐量。 可扩展的去交织器去穿孔器架构也不如传统的不连接的解交织器去穿孔器架构复杂。