公开(公告)号：US5287484A

公开(公告)日：1994-02-15

申请号：US976645

申请日：1992-11-13

申请人： Osamu Nishii ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Takashi Kikuchi ,  Yasuhiko Saigou

发明人： Osamu Nishii ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Takashi Kikuchi ,  Yasuhiko Saigou

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/0897

摘要： A non-shared system with respect to an outside and an inside cache in a multi-processor system has multi-layer hierarchical cache. An invalidation address on a main memory address bus 31 in company with the rewriting of a main memory 30 is transmitted via a first and a second path 35, 36 to inside caches 11,21 so as to invalidate these inside caches 11, 21. The invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and outside caches 12, 22 so as to invalidate these outside caches 12, 22. It is extremely improbable for the address of access for writing to the transmitted to the main memory address bus 31 because the outside caches 12, 22 are operated in either copy back or write once system. As a result, even though the invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and the outside caches 12, 22, it is extremely improbably for the address of access for writing to conflict with a signal on the bidirectional connection.

摘要翻译： 关于多处理器系统中的外部和内部高速缓存的非共享系统具有多层分层高速缓存。 主存储器地址总线31上的与主存储器30的重写有关的无效地址经由第一和第二路径35,36被发送到高速缓存11,21内部，以使这些内部缓存11,21无效。 无效地址通过主存储器地址总线31和外部高速缓存12,22之间的双向连接被发送到外部高速缓存12,22，以使这些外部高速缓存12,22成为无效。对于写入访问地址是非常不可能的 由于外部高速缓存12,22以一个或多个拷贝的一次系统操作，所以传送到主存储器地址总线31。 结果，即使无效地址经由主存储器地址总线31和外部高速缓存12,22之间的双向连接被发送到外部高速缓存12,22，对于写入冲突的访问地址极其不可能 在双向连接上有一个信号。