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    Multi-processor system for invalidating hierarchical cache
    3.
    发明授权
    Multi-processor system for invalidating hierarchical cache 失效
    用于无效分层缓存的多处理器系统

    公开(公告)号：US5287484A

    公开(公告)日：1994-02-15

    申请号：US976645

    申请日：1992-11-13

    申请人： Osamu Nishii ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Takashi Kikuchi ,  Yasuhiko Saigou

    发明人： Osamu Nishii ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Takashi Kikuchi ,  Yasuhiko Saigou

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0811 ,  G06F12/0897

    摘要： A non-shared system with respect to an outside and an inside cache in a multi-processor system has multi-layer hierarchical cache. An invalidation address on a main memory address bus 31 in company with the rewriting of a main memory 30 is transmitted via a first and a second path 35, 36 to inside caches 11,21 so as to invalidate these inside caches 11, 21. The invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and outside caches 12, 22 so as to invalidate these outside caches 12, 22. It is extremely improbable for the address of access for writing to the transmitted to the main memory address bus 31 because the outside caches 12, 22 are operated in either copy back or write once system. As a result, even though the invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and the outside caches 12, 22, it is extremely improbably for the address of access for writing to conflict with a signal on the bidirectional connection.

    摘要翻译： 关于多处理器系统中的外部和内部高速缓存的非共享系统具有多层分层高速缓存。 主存储器地址总线31上的与主存储器30的重写有关的无效地址经由第一和第二路径35,36被发送到高速缓存11,21内部，以使这些内部缓存11,21无效。 无效地址通过主存储器地址总线31和外部高速缓存12,22之间的双向连接被发送到外部高速缓存12,22，以使这些外部高速缓存12,22成为无效。对于写入访问地址是非常不可能的 由于外部高速缓存12,22以一个或多个拷贝的一次系统操作，所以传送到主存储器地址总线31。 结果，即使无效地址经由主存储器地址总线31和外部高速缓存12,22之间的双向连接被发送到外部高速缓存12,22，对于写入冲突的访问地址极其不可能 在双向连接上有一个信号。

    Semiconductor integrated circuit device
    4.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US06879188B2

    公开(公告)日：2005-04-12

    申请号：US10322594

    申请日：2002-12-19

    申请人： Masayuki Miyazaki ,  Ken Tatezawa ,  Kiwamu Takada ,  Kunio Uchiyama ,  Osamu Nishii ,  Kiyoshi Hasegawa ,  Hirokazu Aoki ,  Masaru Kokubo

    发明人： Masayuki Miyazaki ,  Ken Tatezawa ,  Kiwamu Takada ,  Kunio Uchiyama ,  Osamu Nishii ,  Kiyoshi Hasegawa ,  Hirokazu Aoki ,  Masaru Kokubo

    IPC分类号： G06F1/04 ,  G06F1/06 ,  G06F1/32 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H03L7/07 ,  H03L7/081 ,  H03L7/099 ,  H03B19/00

    CPC分类号： H03L7/07 ,  G06F1/04 ,  G06F1/3203 ,  H03L7/0812 ,  H03L7/0995 ,  Y02D10/126

    摘要： A semiconductor integrated circuit device employing two clock signal generating circuits which output clock signals for distribution to an internal circuit of the device, the first and second clock signal generating circuits having different clock-settling times and the selection thereof is effected from outside of the device. A first one of the clock signal generating circuits uses, for example, a phase-locked loop circuit which has a large clock-settling time, and the second clock signal generating circuit is implemented, for example, using a delay-locked loop circuit whose clock-settling time is small, for example, 2-3 periods. Due to the selective actuation of the second clock signal generating circuit, which has a small clock-settling time, the generating of clock signals for the internal circuits can also be halted when the internal circuits of the device are halted thereby to further lower power consumption without compromising clock oscillator responsiveness.

    摘要翻译： 一种采用两个时钟信号发生电路的半导体集成电路器件，其输出时钟信号以分配到器件的内部电路，具有不同时钟稳定时间的第一和第二时钟信号发生电路及其选择是从器件外部实现的 。 时钟信号发生电路中的第一个使用例如具有大的时钟稳定时间的锁相环电路，并且第二时钟信号发生电路例如使用延迟锁定环电路来实现， 时钟建立时间很小，例如2-3个周期。 由于具有小的时钟建立时间的第二时钟信号产生电路的选择性致动，当器件的内部电路停止时也可以停止内部电路的时钟信号的产生，从而进一步降低功耗 而不会影响时钟振荡器的响应。

    Semiconductor integrated circuit device
    5.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US06515519B1

    公开(公告)日：2003-02-04

    申请号：US09580646

    申请日：2000-05-30

    申请人： Masayuki Miyazaki ,  Ken Tatezawa ,  Kiwamu Takada ,  Kunio Uchiyama ,  Osamu Nishii ,  Kiyoshi Hasegawa ,  Hirokazu Aoki ,  Masaru Kokubo

    发明人： Masayuki Miyazaki ,  Ken Tatezawa ,  Kiwamu Takada ,  Kunio Uchiyama ,  Osamu Nishii ,  Kiyoshi Hasegawa ,  Hirokazu Aoki ,  Masaru Kokubo

    IPC分类号： H03B1900

    CPC分类号： H03L7/07 ,  G06F1/04 ,  G06F1/3203 ,  H03L7/0812 ,  H03L7/0995 ,  Y02D10/126

    摘要： A signal from a crystal resonator or an external clock signal are input from terminals xta1 or exta1, and the signal from the crystal resonator or external clock signal are selected by mode terminal mod8 and input to an oscillator OSC. An input clock signal ckl1 is frequency-divided to desired values by a divider DIV1. A divided clock signal clk2 is input as the reference clock of a phase-locked loop PLL1 or delay-locked loop DLL1, and a clock signal output by a circuit selected by a selector SEL3 passes via a divider DIV2 to be distributed to an LSI. The phase-locked loop PLL1 has a clock settling time of at least 40 clock periods, whereas the clock settling time of the delay-locked loop DLL1 is 2-3 periods.

    摘要翻译： 来自晶体谐振器或外部时钟信号的信号从端子xta1或exta1输入，并且来自晶体谐振器或外部时钟信号的信号由模式端子mod8选择并输入到振荡器OSC。 输入时钟信号ck11由分频器DIV1分频为期望值。 输入分频时钟信号clk2作为锁相环路PLL1或延迟锁定环路DLL1的基准时钟，由选择器SEL3选择的电路输出的时钟信号通过分配器DIV2通过分配给LSI。 锁相环PLL1具有至少40个时钟周期的时钟建立时间，而延迟锁定环DLL1的时钟建立时间为2-3个周期。

    Multiprocessor cache system having three states for generating invalidating signals upon write accesses
    6.
    发明授权
    Multiprocessor cache system having three states for generating invalidating signals upon write accesses 失效
    具有三种状态的多处理器缓存系统，用于在写访问时产生无效信号

    公开(公告)号：US5283886A

    公开(公告)日：1994-02-01

    申请号：US950746

    申请日：1992-09-24

    申请人： Osamu Nishii ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Kanji Oishi ,  Jun Kitano ,  Susumu Hatano

    发明人： Osamu Nishii ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Kanji Oishi ,  Jun Kitano ,  Susumu Hatano

    IPC分类号： G06F12/08 ,  G06F12/12

    CPC分类号： G06F12/0833

    摘要： Herein disclosed is a multiprocessor system which comprises first and second processors (1001 and 1002), first and second cache memories (100:#1 and #2), an address bus (123), a data bus (126), an invalidating signal line (PURGE:131) and a main memory (1004). The first and second cache memories are operated by the copy-back method. The state of the data of the first cache (100:#1) exists in one state selected from a group consisting of an invalid first state, a valid and non-updated second state and a valid and updated third state. The second cache (100:#2) is constructed like the first cache. When the write access of the first processor hits the first cache, the state of the data of the first cache is shifted from the second state to the third state, and the first cache outputs the address of the write hit and the invalidating signal to the address bus and the invalidating signal line, respectively. When the write access from the first processor misses the first cache, a data of one block is block-transferred from the main memory to the first cache, and the invalidating signal is outputted. After this, the first cache executes the write of the data in the transfer block. In case the first and second caches hold the data in the third state relating to the pertinent address when an address of an access request is fed to the address bus (123), the pertinent cache writes back the pertinent data in the main memory.

    摘要翻译： 这里公开了一种多处理器系统，其包括第一和第二处理器（1001和1002），第一和第二高速缓冲存储器（100：＃1和＃2），地址总线（123），数据总线（126），无效信号 线（PURGE：131）和主存储器（1004）。 第一和第二高速缓存存储器通过复制方法操作。 第一高速缓存（100：＃1）的数据的状态存在于从由无效的第一状态，有效和未更新的第二状态以及有效和更新的第三状态组成的组中选择的一个状态中。 第二个缓存（100：＃2）被构造成像第一个缓存。 当第一处理器的写入访问第一高速缓存时，第一高速缓存的数据的状态从第二状态转移到第三状态，并且第一高速缓存将写入命中的地址和无效信号输出到 地址总线和无效信号线。 当来自第一处理器的写访问错过第一高速缓存时，一个块的数据被从主存储器块传输到第一高速缓存，并且输出无效信号。 之后，第一个缓存执行传输块中数据的写入。 在第一和第二高速缓冲存储器将存取请求地址与相关地址相关的第三状态的数据保存到地址总线（123）的情况下，相关高速缓冲存储器将相关数据写回到主存储器中。

    SUBSTRATE BIAS SWITCHING UNIT FOR A LOW POWER PROCESSOR
    7.
    发明申请
    SUBSTRATE BIAS SWITCHING UNIT FOR A LOW POWER PROCESSOR 失效
    用于低功率处理器的基板偏置开关单元

    公开(公告)号：US20100005324A1

    公开(公告)日：2010-01-07

    申请号：US12346268

    申请日：2008-12-30

    申请人： Yonetaro TOTSUKA ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

    发明人： Yonetaro TOTSUKA ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

    摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

    摘要翻译： 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

    Processor system using synchronous dynamic memory
    8.
    发明授权
    Processor system using synchronous dynamic memory 失效

    公开(公告)号：US07143230B2

    公开(公告)日：2006-11-28

    申请号：US10752569

    申请日：2004-01-08

    申请人： Kunio Uchiyama ,  Osamu Nishii

    发明人： Kunio Uchiyama ,  Osamu Nishii

    IPC分类号： G06F12/00

    CPC分类号： G11C8/18 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  H04N19/423 ,  H04N19/61

    摘要： A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.

    Data processor and data processor system having multiple modes of address indexing and operation
    9.
    发明授权
    Data processor and data processor system having multiple modes of address indexing and operation 有权
    数据处理器和数据处理器系统具有多种地址索引和操作模式

    公开(公告)号：US06532528B1

    公开(公告)日：2003-03-11

    申请号：US09563753

    申请日：2000-05-01

    申请人： Junichi Nishimoto ,  Osamu Nishii ,  Fumio Arakawa ,  Susumu Narita ,  Masayuki Ito ,  Makoto Toda ,  Kunio Uchiyama

    发明人： Junichi Nishimoto ,  Osamu Nishii ,  Fumio Arakawa ,  Susumu Narita ,  Masayuki Ito ,  Makoto Toda ,  Kunio Uchiyama

    IPC分类号： G06F1210

    CPC分类号： G06F12/1027 ,  G06F2212/652

    摘要： A data processor in which a speed of an address translating operation is raised is disclosed. A translation lookaside buffer is divided into a buffer for data and a buffer for instruction, address translation information for instruction is also stored into a translation lookaside buffer for data, and when a translation miss occurs in a translation lookaside buffer for instruction, new address translation information is fetched from the translation lookaside buffer for data. A high speed of the address translating operation can be realized as compared with that in case of obtaining address translation information from an external address translation table each time a translation miss occurs in the translation lookaside buffer for instruction.

    摘要翻译： 公开了一种提高地址转换操作速度的数据处理器。 翻译后备缓冲区被分为用于数据的缓冲器和用于指令的缓冲器，用于指令的地址转换信息也被存储到用于数据的翻译后备缓冲器中，并且当用于指令的翻译后备缓冲器中发生翻译错误时，新的地址转换 从数据的翻译后备缓冲区中提取信息。 与每次在用于指令的翻译后备缓冲器中发生翻译缺口时从外部地址转换表获得地址转换信息的情况相比，可以实现地址转换操作的高速度。