公开(公告)号：US11722689B2

公开(公告)日：2023-08-08

申请号：US17318625

申请日：2021-05-12

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N11/02 ,  H04N19/52 ,  H04N19/176 ,  H04N19/186

CPC classification number: H04N19/52 ,  H04N19/176 ,  H04N19/186

Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: stores MV information and correction processing information into a FIFO buffer for an HMVP mode in association, the MV information being derived for a processed block and correction processing information being related to correction processing of a prediction image of the processed block; registers, in a prediction candidate list for a merge mode, one or more prediction candidates each being a combination of MV information and correction processing information, the prediction candidates including a prediction candidate which is a combination of the motion vector information and the correction processing information stored in the FIFO buffer; and selects a prediction candidate from the prediction candidate list when a current block is to be processed in the merge mode, and performs correction processing of a prediction image of the current block, based on the correction processing information.

公开(公告)号：US11716492B2

公开(公告)日：2023-08-01

申请号：US17832520

申请日：2022-06-03

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi Kanoh ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N11/02 ,  H04N19/96 ,  H04N19/124 ,  H04N19/159 ,  H04N19/176 ,  H04N19/18 ,  H04N19/66 ,  H04N19/91

CPC classification number: H04N19/96 ,  H04N19/124 ,  H04N19/159 ,  H04N19/176 ,  H04N19/18 ,  H04N19/66 ,  H04N19/91

Abstract: An image decoder performs a first partitioning including using a first partition mode, without parsing first splitting information indicative of the first partition mode, to split a first block into a plurality of second blocks in response to that the first block is located adjacent to an edge of a picture and that the dimensions of the first block satisfy a first condition; and performs a second partitioning on the second block by parsing second splitting information indicative of a second partition mode, wherein the second partition mode allows at least one of a quad tree splitting and a binary splitting, and using the second partition mode to split the second block into a plurality of coding units (CUs), wherein the second partition mode prohibits the quad tree splitting of the second block in response to that the second block is located adjacent to the edge of the picture.

公开(公告)号：US11695489B2

公开(公告)日：2023-07-04

申请号：US16990570

申请日：2020-08-11

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Noritaka Iguchi ,  Tadamasa Toma ,  Hisaya Katou

IPC: H04J3/06 ,  H04N21/2381 ,  H04N21/242 ,  H04N21/434 ,  H04N21/643 ,  H04N21/854 ,  H04L45/74 ,  H04L69/04

CPC classification number: H04J3/0635 ,  H04L45/74 ,  H04L69/04 ,  H04N21/2381 ,  H04N21/242 ,  H04N21/434 ,  H04N21/64322 ,  H04N21/85406

Abstract: A transmission method includes generating one or more frames for content transfer using IP packets, and transmitting the one or more generated frames by broadcast. Each of the one or more frames contains a plurality of second transfer units, each of the plurality of second transfer units contains one or more first transfer units, each of the one or more first transfer units contains at least one of the IP packets, an object IP packet of the IP packets contains first reference clock information indicating time for reproduction of the content in data structure different from MMT packet data structure, the object IP packet being stored in a first transfer unit positioned at a head in the one or more frames, the one or more frames contains control information storing second reference clock information indicating time for reproduction of the content, and header compression processing on the object IP packet is omitted.

公开(公告)号：US11689739B2

公开(公告)日：2023-06-27

申请号：US17389010

申请日：2021-07-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Ryuichi Kanoh

IPC: H04N19/52 ,  H04N19/157 ,  H04N19/176 ,  H04N19/182 ,  H04N19/59

CPC classification number: H04N19/52 ,  H04N19/157 ,  H04N19/176 ,  H04N19/182 ,  H04N19/59

Abstract: An encoder includes memory and circuitry configured to determine a merge mode to be applied to a current block, wherein the merge mode includes a sub-block merge mode and a first merge mode. In the merge mode, inter-prediction parameters are inferred from a neighboring block neighboring the current block. In the sub-block merge mode, the current block includes a plurality of sub-blocks, and inter-prediction parameters are provided for each of the plurality of sub-blocks. When the merge mode is determined to be the first merge mode, the circuitry generates a prediction image for the current block by performing a bi-directional optical flow prediction process, wherein the bi-directional optical flow prediction process uses a spatial gradient for the current block. When the merge mode is determined to be the sub-block merge mode, the circuitry generates a prediction image for the current block by not performing the bi-directional optical flow prediction process.

公开(公告)号：US11689714B2

公开(公告)日：2023-06-27

申请号：US17368123

申请日：2021-07-06

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/105 ,  H04N19/176 ,  H04N19/182

CPC classification number: H04N19/105 ,  H04N19/176 ,  H04N19/182

Abstract: An encoder includes circuitry and memory connected to the circuitry. The circuitry, in operation: derives, as a first parameter, a total sum of absolute values of sums of horizontal gradient values respectively for pairs of relative pixel positions; derives, as a second parameter, a total sum of absolute values of sums of vertical gradient values respectively for the pairs of relative pixel positions; derives, as a third parameter, a total sum of horizontal-related pixel difference values respectively for the pairs of relative pixel positions; derives, as a fourth parameter, a total sum of vertical-related pixel difference values respectively for the pairs of relative pixel positions; derives, as a fifth parameter, a total sum of vertical-related sums of horizontal gradient values respectively for the pairs of relative pixel positions; and generates a prediction image to be used to encode the current block using the first, second, third, fourth, and fifth parameters.

公开(公告)号：US11677947B2

公开(公告)日：2023-06-13

申请号：US17377107

申请日：2021-07-15

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/124 ,  H04N19/136 ,  H04N19/157 ,  H04N19/176 ,  H04N19/61

CPC classification number: H04N19/124 ,  H04N19/136 ,  H04N19/157 ,  H04N19/176 ,  H04N19/61

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: performs quantization on a plurality of transform coefficients of a current block to be encoded, using a quantization matrix when orthogonal transform is performed on the current block and secondary transform is not performed on the current block; and performs quantization on the plurality of transform coefficients of the current block without using the quantization matrix when orthogonal transform is not performed on the current block and when both orthogonal transform and secondary transform are performed on the current block.

公开(公告)号：US11665355B2

公开(公告)日：2023-05-30

申请号：US17520137

申请日：2021-11-05

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh

IPC: H04N19/159 ,  H04N19/105 ,  H04N19/176 ,  H04N19/186 ,  H04N19/583

CPC classification number: H04N19/159 ,  H04N19/105 ,  H04N19/176 ,  H04N19/186 ,  H04N19/583

Abstract: An encoder includes memory, and circuitry accessible to the memory. The circuitry accessible to the memory: determines whether OBMC is applicable to generation of a prediction image of a current block, according to whether BIO is to be applied to the generation of the prediction image of the current block; when BIO is to be applied to the generation of the prediction image of the current block, determines that OBMC is not applicable to the generation of the prediction image of the current block, and applies BIO to the generation of the prediction image of the current block without applying OBMC.

公开(公告)号：US11652990B2

公开(公告)日：2023-05-16

申请号：US17530199

申请日：2021-11-18

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi Kanoh ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/14 ,  H04N19/117 ,  H04N19/159 ,  H04N19/174

CPC classification number: H04N19/117 ,  H04N19/14 ,  H04N19/159 ,  H04N19/174

Abstract: An encoder includes processing circuitry and a memory coupled to the processing circuitry. The processing circuitry is configured to: select a filter based at least on a prediction mode used for a first block, the filter including first filter coefficients for the first block and second filter coefficients for a second block; multiply values of first pixels among the first block and second pixels among the second block by the first filter coefficients to change a value of a first pixel in the first pixels; and multiply the values of the first pixels among the first block and the second pixels among the second block by the second filter coefficients to change a value of a second pixel in the second pixels.

公开(公告)号：US20230119758A1

公开(公告)日：2023-04-20

申请号：US18071370

申请日：2022-11-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya LI ,  Chong Soon LIM ,  Hai Wei SUN ,  Han Boon TEO ,  Che Wei KUO ,  Chu Tong WANG ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa Toma ,  Yusuke KATO

IPC: H04N19/117 ,  H04N19/105 ,  H04N19/119 ,  H04N19/82 ,  H04N19/13 ,  H04N19/18 ,  H04N19/186 ,  H04N19/124

Abstract: An encoder includes circuitry and memory. The circuitry, in operation, generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component. The circuitry generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component. The circuitry generates a third coefficient value by adding the first coefficient value to the second coefficient value, and encodes a third reconstructed image sample of the chroma component using the third coefficient value. In the CCALF process, in response to a coordinate of the second reconstructed image sample being (x, y), coordinates of the first reconstructed image samples are (2x, 2y−1), (2x−1, 2y), (2x, 2y), (2x+1, 2y), (2x−1, 2y+1), (2x, 2y+1), (2x+1, 2y+1), and (2x, 2y+2).

公开(公告)号：US11563969B2

公开(公告)日：2023-01-24

申请号：US17506443

申请日：2021-10-20

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Chong Soon Lim ,  Ru Ling Liao ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Han Boon Teo ,  Jing Ya Li

IPC: H04N19/51 ,  H04N19/176 ,  H04N19/182

Abstract: An encoder includes circuitry and a memory coupled to the circuitry, wherein the circuitry, in operation, performs a partition process. The partition process includes calculating first values of a set of pixels between a first partition and a second partition in a current block, using a first motion vector for the first partition; calculating second values of the set of pixels, using a second motion vector for the second partition; and calculating third values of the set of pixels by weighting the first values and the second values. When a ratio of a width to a height of the current block is larger than 4 or a ratio of the height to the width of the current block is larger than 4, the circuitry disables the partition process.