公开(公告)号：US20210210497A1

公开(公告)日：2021-07-08

申请号：US16737088

申请日：2020-01-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Seung-Yeul YANG ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Adarsh RAJASHEKHAR ,  Rahul SHARANGPANI

IPC: H01L27/11514 ,  H01L49/02 ,  H01L45/00 ,  H01L23/528 ,  H01L27/11504

Abstract: A ferroelectric tunnel junction memory device includes a bit line, a word line and a memory cell located between the bit line and the word line. The memory cell includes a ferroelectric tunneling dielectric portion and an ovonic threshold switch material portion.

公开(公告)号：US20210082955A1

公开(公告)日：2021-03-18

申请号：US16568668

申请日：2019-09-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Rahul SHARANGPANI ,  Seung-Yeul YANG ,  Fei ZHOU

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159

Abstract: A three-dimensional ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where each of the electrically conductive layers contains a transition metal element-containing conductive liner and a conductive fill material portion, a vertical semiconductor channel extending vertically through the alternating stack, a vertical stack of tubular transition metal element-containing conductive spacers laterally surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers, and a ferroelectric material layer located between the vertical stack of tubular transition metal element-containing conductive spacers and the transition metal element-containing conductive liner.

公开(公告)号：US20200168619A1

公开(公告)日：2020-05-28

申请号：US16200115

申请日：2018-11-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei ZHOU ,  Adarsh RAJASHEKHAR ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA

IPC: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522

Abstract: In-process source-level material layers including a source-level sacrificial layer are formed over a substrate. An alternating stack of insulating layers and sacrificial material layers is formed over the in-process source-level material layers. A memory opening is formed through the alternating stack, and is filled with a memory film and a sacrificial opening fill structure. The source-level sacrificial layer is replaced with a source contact layer including a doped polycrystalline semiconductor material. The source contact layer can be formed by diffusing a metal in a metallic catalyst material through a semiconductor fill material layer that fills a source cavity formed by removal of the source-level sacrificial layer. The sacrificial opening fill structure is replaced with a vertical semiconductor channel, which can be formed with large grains due to large crystal sizes in the source contact layer. The sacrificial material layers are replaced with electrically conductive layers.