-
1.发明公开公开(公告)号：US20240276725A1
公开(公告)日：2024-08-15
申请号：US18616682
申请日：2024-03-26
IPC分类号： H10B43/27
CPC分类号： H10B43/27
摘要： A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, each including a respective vertical semiconductor channel and a vertical stack of memory elements, a contact via structure contacting a reference electrically conductive layer that is one of the electrically conductive layers, and at least one silicon oxide liner laterally surrounding a cylindrical portion of the contact via structure and contacting a laterally protruding portion of the contact via structure.
-
2.发明公开公开(公告)号：US20230157013A1
公开(公告)日：2023-05-18
申请号：US17525233
申请日：2021-11-12
IPC分类号： H01L27/11556 , H01L27/11582 , H01L21/768
CPC分类号： H01L27/11556 , H01L21/76802 , H01L21/76829 , H01L27/11582
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, etch stop plates located in the staircase region, laterally and vertically spaced apart among one another, and overlying an end portion of a respective one of the electrically conductive layers, and contact via structures located in a staircase region, vertically extending through a respective one of the etch stop plates, and contacting a respective one of the electrically conductive layers.
-
3.发明申请公开(公告)号：US20230090951A1
公开(公告)日：2023-03-23
申请号：US17479637
申请日：2021-09-20
IPC分类号： H01L23/522 , H01L23/535 , H01L23/528 , H01L23/532 , H01L21/768
摘要： A semiconductor structure includes semiconductor devices located over a substrate, bit lines electrically connected to the semiconductor devices and having a respective reentrant vertical cross-sectional profile within a vertical plane that is perpendicular to a lengthwise direction along which the bit lines laterally extend, and dielectric portions that are interlaced with the bit lines along a horizontal direction that is perpendicular to the lengthwise direction. The dielectric portions may contain air gaps. A bit-line-contact via structure can be formed on top of a bit line. In some embodiments, dielectric cap strips may be located on top surface of the dielectric portions and may cover peripheral regions of the top surfaces of the bit lines without covering middle regions of the top surfaces of the bit lines.
-
公开(公告)号：US20220139949A1
公开(公告)日：2022-05-05
申请号：US17085735
申请日：2020-10-30
IPC分类号： H01L27/11582 , H01L27/11556 , H01L23/522 , H01L27/11565 , H01L27/1157 , H01L27/11519 , H01L27/11524 , G11C8/14
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Each electrically conductive layer within a subset of the electrically conductive layers includes a respective first metal layer containing an elemental metal and a respective first metal silicide layer containing a metal silicide of the elemental metal. Memory openings vertically extend through the alternating stack. Memory opening fill structures located within the memory openings can include a respective memory film and a respective vertical semiconductor channel.
-
公开(公告)号：US20210375848A1
公开(公告)日：2021-12-02
申请号：US16886221
申请日：2020-05-28
IPC分类号： H01L25/18 , H01L25/065 , H01L23/00 , H01L25/00
摘要： Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have physically exposed surfaces that face downward. A first set of bonding wires can connect a respective pair of front-side external bonding pads, and a second set of bonding wires can connect a respective pair of backside external bonding pads.
-
6.发明申请公开(公告)号：US20210358942A1
公开(公告)日：2021-11-18
申请号：US16877328
申请日：2020-05-18
IPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L27/11543 , H01L27/11524 , H01L27/11556 , H01L27/11519
摘要： A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening through the alternating stack, forming lateral recesses at levels of the sacrificial material layers around the memory opening, forming a vertical stack of discrete clam-shaped semiconductor liners in the lateral recesses, replacing the vertical stack of discrete clam-shaped semiconductor liners with a vertical stack of inner clam-shaped metallic liners, forming a vertical stack of discrete charge storage elements on the vertical sack of inner clam-shaped metallic liners, forming a tunneling dielectric layer and a vertical semiconductor channel over the vertical stack of discrete charge storage elements and the vertical stack of inner clam-shaped metallic liners, and replacing each of the sacrificial material layers with an electrically conductive layer.
-
公开(公告)号：US20210358931A1
公开(公告)日：2021-11-18
申请号：US16876877
申请日：2020-05-18
发明人： Raghuveer S. MAKALA , Yanli ZHANG , Fei ZHOU , Rahul SHARANGPANI , Adarsh RAJASHEKHAR , Seung-Yeul YANG
IPC分类号： H01L27/11556 , H01L27/11519 , H01L27/11524 , H01L27/11597 , H01L27/11539
摘要： A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel.
-
8.发明申请公开(公告)号：US20200335487A1
公开(公告)日：2020-10-22
申请号：US16917526
申请日：2020-06-30
IPC分类号： H01L25/18 , H01L29/04 , H01L29/16 , H01L27/11556 , H01L27/11529 , H01L27/11582 , H01L27/11573 , H01L25/065 , H01L25/00 , H01L23/00
摘要： A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry.
-
公开(公告)号：US20200152655A1
公开(公告)日：2020-05-14
申请号：US16183920
申请日：2018-11-08
IPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11565 , H01L21/768
摘要： A vertical repetition of a unit layer stack including an insulating layer, a sacrificial material layer, and a nucleation promoter layer is formed over a substrate. Memory stack structures are formed through the vertical repetition. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers and the nucleation promoter layers within the vertical repetition. Electrically conductive layers are formed in the backside recesses by selectively growing a metallic material from physically exposed surfaces of the nucleation promoter layers while suppressing growth of the metallic material from physically exposed surfaces of the insulating layers.
-
10.发明公开公开(公告)号：US20240008281A1
公开(公告)日：2024-01-04
申请号：US17809758
申请日：2022-06-29
IPC分类号： H01L27/11597 , H01L27/1159
CPC分类号： H01L27/11597 , H01L27/1159
摘要： A ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening extending vertically through the alternating stack and including laterally-protruding portions at levels of the electrically conductive layers, and a memory opening fill structure located in the memory opening and containing a vertical semiconductor channel and a vertical stack of discrete ferroelectric memory structures located in the laterally-protruding portions of the memory opening. Each of the ferroelectric memory structures includes crystalline ferroelectric material portion and a crystalline template material portion located between a respective electrically conductive layer of the electrically conductive layers and the crystalline ferroelectric material portion.
-
-
-
-
-
-
-
-
-
搜索结果
53 条记录 (耗时 0.024 秒)
