公开(公告)号：US20210358931A1

公开(公告)日：2021-11-18

申请号：US16876877

申请日：2020-05-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. MAKALA ,  Yanli ZHANG ,  Fei ZHOU ,  Rahul SHARANGPANI ,  Adarsh RAJASHEKHAR ,  Seung-Yeul YANG

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11597 ,  H01L27/11539

Abstract: A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel.

公开(公告)号：US20210358952A1

公开(公告)日：2021-11-18

申请号：US16876816

申请日：2020-05-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. Makala ,  Yanli ZHANG ,  Fei ZHOU ,  Rahul SHARANGPANI ,  Adarsh RAJASHEKHAR ,  Seung-Yeul YANG

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159 ,  H01L23/522 ,  H01L23/528

Abstract: A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel.

公开(公告)号：US20220157966A1

公开(公告)日：2022-05-19

申请号：US17097841

申请日：2020-11-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bhagwati PRASAD ,  Joyeeta NAG ,  Seung-Yeul YANG ,  Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA

IPC: H01L29/51 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/78 ,  H01L21/28 ,  H01L21/3115 ,  H01L29/66

Abstract: A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.

公开(公告)号：US20210050372A1

公开(公告)日：2021-02-18

申请号：US16743436

申请日：2020-01-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Yanli ZHANG ,  Seung-Yeul YANG ,  Fei ZHOU

IPC: H01L27/11597 ,  G11C11/22 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A ferroelectric memory device includes a semiconductor channel, a gate electrode, and a ferroelectric memory element located between the semiconductor channel and the gate electrode. The ferroelectric memory element includes at least one ferroelectric material portion and at least one antiferroelectric material portion.

公开(公告)号：US20210050371A1

公开(公告)日：2021-02-18

申请号：US16541289

申请日：2019-08-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Seung-Yeul YANG ,  Fei ZHOU ,  Adarsh RAJASHEKHAR

IPC: H01L27/11597 ,  G11C11/22 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11592

Abstract: A three-dimensional ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where each of the electrically conductive layers contains a respective transition metal nitride liner and a respective conductive fill material layer, a vertical semiconductor channel vertically extending through the alternating stack, a vertical stack of transition metal nitride spacers laterally surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers, and discrete ferroelectric material portions laterally surrounding the respective transition metal nitride spacers and located at the levels of the electrically conductive layers.

公开(公告)号：US20220157852A1

公开(公告)日：2022-05-19

申请号：US17097757

申请日：2020-11-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bhagwati PRASAD ,  Joyeeta NAG ,  Seung-Yeul YANG ,  Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159 ,  H01L29/51 ,  H01L29/66

Abstract: A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.

公开(公告)号：US20210210497A1

公开(公告)日：2021-07-08

申请号：US16737088

申请日：2020-01-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Seung-Yeul YANG ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Adarsh RAJASHEKHAR ,  Rahul SHARANGPANI

IPC: H01L27/11514 ,  H01L49/02 ,  H01L45/00 ,  H01L23/528 ,  H01L27/11504

Abstract: A ferroelectric tunnel junction memory device includes a bit line, a word line and a memory cell located between the bit line and the word line. The memory cell includes a ferroelectric tunneling dielectric portion and an ovonic threshold switch material portion.

公开(公告)号：US20210082955A1

公开(公告)日：2021-03-18

申请号：US16568668

申请日：2019-09-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Rahul SHARANGPANI ,  Seung-Yeul YANG ,  Fei ZHOU

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159

Abstract: A three-dimensional ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where each of the electrically conductive layers contains a transition metal element-containing conductive liner and a conductive fill material portion, a vertical semiconductor channel extending vertically through the alternating stack, a vertical stack of tubular transition metal element-containing conductive spacers laterally surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers, and a ferroelectric material layer located between the vertical stack of tubular transition metal element-containing conductive spacers and the transition metal element-containing conductive liner.