公开(公告)号：US20240306386A1

公开(公告)日：2024-09-12

申请号：US18360474

申请日：2023-07-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yusuke MUKAE ,  Tatsuya HINOUE ,  Raghuveer S. MAKALA ,  Shungo ASAEDA

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming memory openings through the alternating stack, forming memory opening fill structures in the memory openings including respective vertical stack of memory elements and a respective vertical semiconductor channel, forming a lateral isolation trench through the alternating stack, forming lateral recesses by removing the sacrificial material layers selective to the insulating layers and the memory opening fill structures, depositing a first tungsten layer in the lateral recesses using a first tungsten deposition process in which a fluorine-containing tungsten precursor gas is used as a reactant, and depositing a second tungsten layer on the first tungsten layer in the lateral recesses using a second tungsten deposition process in which a fluorine-free tungsten precursor gas is used as a reactant.

公开(公告)号：US20240064995A1

公开(公告)日：2024-02-22

申请号：US18161439

申请日：2023-01-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Kartik SONDHI ,  Rahul SHARANGPANI ,  Fei ZHOU

IPC: H10B51/20 ,  H10B51/30

CPC classification number: H10B51/20 ,  H10B51/30

Abstract: A ferroelectric memory device includes an alternating stack of insulating layers and composite layers that are interlaced along a vertical direction, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and an inner ferroelectric material layer including a first ferroelectric material, and a vertical stack of electrically-non-insulating material portions located between the inner ferroelectric material layer and the composite layers. Each of the composite layers includes a respective electrically conductive layer and a respective outer ferroelectric material layer including a second ferroelectric material, embedding the respective electrically conductive layer, and contacting a respective electrically-non-insulating material portion.

公开(公告)号：US20230171957A1

公开(公告)日：2023-06-01

申请号：US18154286

申请日：2023-01-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei ZHOU ,  Raghuveer S. MAKALA

IPC: H10B41/27 ,  G11C16/04 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A method of forming a memory device includes forming an alternating stack of disposable material layers and silicon nitride layers over a substrate, forming a memory opening through the alternating stack, forming a memory film and a vertical semiconductor channel in the memory opening, where the memory film includes a continuous silicon nitride charge storage material layer and a tunneling dielectric layer, forming a backside trench through the alternating stack, forming laterally-extending cavities by removing the disposable material layers selective to the silicon nitride layers through the backside trench, oxidizing portions of the silicon nitride layers and the continuous silicon nitride charge storage material layer exposed in the laterally-extending cavities to form silicon oxide insulating layers and to separate the continuous silicon nitride charge storage material layer into a vertical stack of discrete silicon nitride charge storage material portions, and replacing remaining portions of the silicon nitride layers with electrically conductive layers.

公开(公告)号：US20230089578A1

公开(公告)日：2023-03-23

申请号：US17479573

申请日：2021-09-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Rahul SHARANGPANI ,  Fei ZHOU

IPC: H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  G11C7/18 ,  H01L23/48

Abstract: A semiconductor structure includes semiconductor devices located over a substrate, bit lines electrically connected to the semiconductor devices and having a respective reentrant vertical cross-sectional profile within a vertical plane that is perpendicular to a lengthwise direction along which the bit lines laterally extend, and dielectric portions that are interlaced with the bit lines along a horizontal direction that is perpendicular to the lengthwise direction. The dielectric portions may contain air gaps. A bit-line-contact via structure can be formed on top of a bit line. In some embodiments, dielectric cap strips may be located on top surface of the dielectric portions and may cover peripheral regions of the top surfaces of the bit lines without covering middle regions of the top surfaces of the bit lines.

公开(公告)号：US20230008286A1

公开(公告)日：2023-01-12

申请号：US17370317

申请日：2021-07-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin HOU ,  Peter RABKIN ,  Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Masaaki HIGASHITANI

IPC: H01L23/00

Abstract: A bonded assembly includes a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads laterally surrounded by a first pad-level dielectric layer. The first pad-level dielectric layer includes at least one first encapsulated airgap located between neighboring pairs of first bonding pads and encapsulated by a first dielectric fill material of the first pad-level dielectric layer. The bonded assembly includes a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads laterally surrounded by a second pad-level dielectric layer. Each of the second bonding pads is bonded to a respective one of the first bonding pads.

公开(公告)号：US20220399354A1

公开(公告)日：2022-12-15

申请号：US17345860

申请日：2021-06-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Adarsh RAJASHEKHAR

IPC: H01L27/11524 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within the memory openings. Each of the electrically conductive layers includes a metallic fill material layer and a plurality of vertical tubular metallic liners laterally surrounding a respective one of the memory opening fill structures and located between the metallic fill material layer and a respective one of the memory opening fill structures. The tubular metallic liners may be formed by selective metal or metal oxide deposition, or by conversion of surface portions of the metallic fill material layers into metallic compound material portions by nitridation, oxidation, or incorporation of boron atoms.

公开(公告)号：US20220238453A1

公开(公告)日：2022-07-28

申请号：US17155541

申请日：2021-01-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fei ZHOU

IPC: H01L23/532 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory stack structures vertically extending through the alternating stack. Each of the memory stack structures includes a respective vertical semiconductor channel and a respective vertical stack of memory elements located at levels of the electrically conductive layers. Each of the electrically conductive layers includes a respective conductive liner comprising molybdenum carbide or carbonitride, and a respective molybdenum metal fill material portion.

公开(公告)号：US20220157852A1

公开(公告)日：2022-05-19

申请号：US17097757

申请日：2020-11-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bhagwati PRASAD ,  Joyeeta NAG ,  Seung-Yeul YANG ,  Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159 ,  H01L29/51 ,  H01L29/66

Abstract: A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.

公开(公告)号：US20220093644A1

公开(公告)日：2022-03-24

申请号：US17543987

申请日：2021-12-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Kartik SONDHI ,  Ramy Nashed Bassely SAID ,  Senaka KANAKAMEDALA

IPC: H01L27/11582 ,  H01L21/28 ,  H01L27/11556 ,  H01L29/423

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel and a memory film. The memory film includes a contoured blocking dielectric layer including sac-shaped lateral protrusions located at levels of the electrically conductive layers, a tunneling dielectric layer in contact with the vertical semiconductor channel, and a vertical stack of charge storage material portions located within volumes enclosed by the sac-shaped lateral protrusions.

公开(公告)号：US20210408031A1

公开(公告)日：2021-12-30

申请号：US16910752

申请日：2020-06-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Adarsh RAJASHEKHAR

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11556

Abstract: A source-level sacrificial layer and an alternating stack of insulating layers and spacer material layers are formed over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and the source-level sacrificial layer, and memory opening fill structures are formed. A source cavity is formed by removing the source-level sacrificial layer, and exposing an outer sidewall of each vertical semiconductor channel in the memory opening fill structures. A metal-containing layer is deposited on physically exposed surfaces of the vertical semiconductor channel and the vertical semiconductor channel is crystallized using metal-induced lateral crystallization. Alternatively or additionally, cylindrical metal-semiconductor alloy regions can be formed around the vertical semiconductor channels to reduce contact resistance. A source contact layer can be formed in the source cavity.