公开(公告)号：US20240064992A1

公开(公告)日：2024-02-22

申请号：US17821012

申请日：2022-08-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Kartik SONDHI ,  Raghuveer S. MAKALA ,  Tiffany SANTOS ,  Fei ZHOU ,  Joyeeta NAG ,  Bhagwati PRASAD

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/11597 ,  H01L27/11587 ,  H01L29/6684 ,  H01L29/78391

Abstract: A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

公开(公告)号：US20230223266A1

公开(公告)日：2023-07-13

申请号：US17573429

申请日：2022-01-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei ZHOU ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Yujin TERASAWA ,  Naoki TAKEGUCHI ,  Kensuke YAMAGUCHI ,  Masaaki HIGASHITANI

IPC: H01L21/285 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11597 ,  H01L27/24 ,  H01L21/768 ,  C23C16/14 ,  C23C16/455

CPC classification number: H01L21/28568 ,  C23C16/14 ,  C23C16/45525 ,  H01L21/76876 ,  H01L27/2481 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11597 ,  H01L21/76846

Abstract: A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.

公开(公告)号：US20230129594A1

公开(公告)日：2023-04-27

申请号：US17566262

申请日：2021-12-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fumitaka AMANO

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535

Abstract: A semiconductor structure includes a first dielectric material layer, a first metal interconnect structure embedded within the first dielectric material layer and including a first metallic material portion including a first metal, a second dielectric material layer located over the first dielectric material layer, and a second metal interconnect structure embedded within the second dielectric material layer and including an integrated line-and-via structure that includes a second metallic material portion including a second metal. A metal-semiconductor alloy portion including a first metal-semiconductor alloy of the first metal and a semiconductor material is located underneath the second metallic material portion, and contacts a top surface of the first metal interconnect structure.

公开(公告)号：US20220399350A1

公开(公告)日：2022-12-15

申请号：US17345831

申请日：2021-06-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Adarsh RAJASHEKHAR

IPC: H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within the memory openings. Each of the electrically conductive layers includes a metallic fill material layer and a plurality of vertical tubular metallic liners laterally surrounding a respective one of the memory opening fill structures and located between the metallic fill material layer and a respective one of the memory opening fill structures. The tubular metallic liners may be formed by selective metal or metal oxide deposition, or by conversion of surface portions of the metallic fill material layers into metallic compound material portions by nitridation, oxidation, or incorporation of boron atoms.

公开(公告)号：US20220223470A1

公开(公告)日：2022-07-14

申请号：US17657521

申请日：2022-03-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Roshan Jayakhar TIRUKKONDA ,  Monica TITUS ,  Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA ,  Rahul SHARANGPANI ,  Adarsh RAJASHEKAR

IPC: H01L21/768 ,  H01L21/306

Abstract: A method of forming a structure includes forming an alternating stack of first material layers and second material layers over a substrate, forming a mask layer over the alternating stack, forming a cavity in the mask layer, forming a first cladding liner on a sidewall of the cavity in the mask layer, and forming a via opening the alternating stack by performing an anisotropic etch process that transfers a pattern of the cavity in the mask layer through the alternating stack using a combination of the first cladding liner and the mask layer as an etch mask.

公开(公告)号：US20220093555A1

公开(公告)日：2022-03-24

申请号：US17542963

申请日：2021-12-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin HOU ,  Peter RABKIN ,  Yangyin CHEN ,  Masaaki HIGASHITANI ,  Rahul SHARANGPANI

IPC: H01L23/00

Abstract: A method of forming a bonded assembly includes providing a first semiconductor die containing and first metallic bonding structures and a first dielectric capping layer containing openings and contacting distal horizontal surfaces of the first metallic bonding structures, providing a second semiconductor die containing second metallic bonding structures, disposing the second semiconductor die in contact with the first semiconductor die, and annealing the second semiconductor die in contact with the first semiconductor die such that a metallic material of at least one of the first metallic bonding structures and the second metallic bonding structures expands to fill the openings in the first dielectric capping layer to bond at least a first subset of the first metallic bonding structures to at least a first subset of the second metallic bonding structures.

公开(公告)号：US20210296284A1

公开(公告)日：2021-09-23

申请号：US16825304

申请日：2020-03-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Adarsh RAJASHEKHAR ,  Senaka KANAKAMEDALA ,  Fei ZHOU

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: A first semiconductor die includes first semiconductor devices located over a first substrate, first interconnect-level dielectric material layers embedding first metal interconnect structures and located on the first semiconductor devices, and a first pad-level dielectric layer located on the first interconnect-level dielectric material layers and embedding first bonding pads. Each of the first bonding pads includes a first proximal horizontal surface and at least one first distal horizontal surface that is more distal from the first substrate than the first proximal horizontal surface is from the first substrate and has a lesser total area than a total area of the first proximal horizontal surface. A second semiconductor die including second bonding pads that are embedded in a second pad-level dielectric layer can be bonded to a respective distal surface of the first bonding pads.

公开(公告)号：US20210242241A1

公开(公告)日：2021-08-05

申请号：US17237447

申请日：2021-04-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Rahul SHARANGPANI

IPC: H01L27/11597 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/76

Abstract: A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, a memory opening vertically extending through the alternating stack, a vertical word line located in the memory opening and vertically extending through each of the source layers and the drain layers of the alternating stack, discrete semiconductor channels contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source layers and a drain layer of the drain layers, and a vertical stack of discrete memory material portions laterally surrounding the vertical word line.

公开(公告)号：US20190287982A1

公开(公告)日：2019-09-19

申请号：US16020088

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tatsuya HINOUE ,  Tomoyuki OBU ,  Tomohiro UNO ,  Yusuke MUKAE ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Adarsh RAJASHEKHAR

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11529 ,  H01L27/11573

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each of the electrically conductive layers includes a stack of a compositionally graded diffusion barrier and a metal fill material portion, and the compositionally graded diffusion barrier includes a substantially amorphous region contacting the interface between the compositionally graded diffusion barrier and a substantially crystalline region that is spaced from the interface by the amorphous region. The substantially crystalline region effectively blocks atomic diffusion, and the amorphous region induces formation of large grains during deposition of the metal fill material portions.

公开(公告)号：US20160293617A1

公开(公告)日：2016-10-06

申请号：US15177737

申请日：2016-06-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Thomas Jongwan KWON ,  Senaka KANAKAMEDALA ,  George MATAMIS

IPC: H01L27/115 ,  H01L21/285 ,  H01L29/788 ,  H01L21/311 ,  H01L21/3205 ,  H01L29/423 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L27/11556 ,  G11C16/0408 ,  G11C16/06 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02238 ,  H01L21/28273 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/31111 ,  H01L21/32055 ,  H01L27/11519 ,  H01L27/11524 ,  H01L29/42332 ,  H01L29/7883

Abstract: A method of making a monolithic three dimensional NAND string which contains a semiconductor channel and a plurality of control gate electrodes, includes selectively forming a plurality of discrete charge storage regions using atomic layer deposition. The plurality of discrete charge storage regions includes at least one of a metal or an electrically conductive metal oxide.

Abstract translation: 包括半导体通道和多个控制栅电极的单片三维NAND串的制造方法包括使用原子层沉积选择性地形成多个离散的电荷存储区域。 多个离散电荷存储区域包括金属或导电金属氧化物中的至少一种。