公开(公告)号：US12032497B2

公开(公告)日：2024-07-09

申请号：US17469769

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Hongzhong Zheng ,  Dimin Niu ,  Peng Gu

IPC: G06F13/16 ,  G06F7/544 ,  G06F9/30

CPC classification number: G06F13/1652 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30036 ,  G06F13/1694

Abstract: A high bandwidth memory (HBM) system includes a first HBM+ card. The first HBM+ card includes a plurality of HBM+ cubes. Each HBM+ cube has a logic die and a memory die. The first HBM+ card also includes a HBM+ card controller coupled to each of the plurality of HBM+ cubes and configured to interface with a host, a pin connection configured to connect to the host, and a fabric connection configured to connect to at least one HBM+ card.

公开(公告)号：US20240086292A1

公开(公告)日：2024-03-14

申请号：US18513111

申请日：2023-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Wenqin Huangfu

IPC: G06F11/30 ,  G06F11/34

CPC classification number: G06F11/3037 ,  G06F11/3428

Abstract: A method for computing. In some embodiments, the method includes: calculating an advantage score of a first computing task, the advantage score being a measure of an extent to which a plurality of function in memory circuits is capable of executing the first computing task more efficiently by than one or more extra-memory processing circuits, the first computing task including instructions and data; in response to determining that the advantage score of the first computing task is less than a first threshold, executing the first computing task by the one or more extra-memory processing circuits; and in response to determining that the first computing task is at least equal to the first threshold: compiling the instructions for execution by the function in memory circuits; formatting the data for the function in memory circuits; and executing the first computing task, by the function in memory circuits.

公开(公告)号：US11853186B2

公开(公告)日：2023-12-26

申请号：US17699679

申请日：2022-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Wenqin Huangfu

IPC: G06F11/30 ,  G06F11/34

CPC classification number: G06F11/3037 ,  G06F11/3428

Abstract: A method for computing. In some embodiments, the method includes: calculating an advantage score of a first computing task, the advantage score being a measure of an extent to which a plurality of function in memory circuits is capable of executing the first computing task more efficiently by than one or more extra-memory processing circuits, the first computing task including instructions and data; in response to determining that the advantage score of the first computing task is less than a first threshold, executing the first computing task by the one or more extra-memory processing circuits; and in response to determining that the first computing task is at least equal to the first threshold: compiling the instructions for execution by the function in memory circuits; formatting the data for the function in memory circuits; and executing the first computing task, by the function in memory circuits.

公开(公告)号：US20230367711A1

公开(公告)日：2023-11-16

申请号：US18357798

申请日：2023-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Andrew Chang ,  Ehsan Najafabadi

IPC: G06F12/06 ,  G06F9/30 ,  G06F13/42 ,  G06F9/445 ,  G06F12/0891 ,  G06F13/16

CPC classification number: G06F12/0646 ,  G06F9/30047 ,  G06F13/4234 ,  G06F9/44505 ,  G06F12/0891 ,  G06F13/1668

Abstract: Provided are systems, methods, and apparatuses for providing a storage resource. The method can include: operating a first controller coupled to a network interface in accordance with a cache coherent protocol; performing at least one operation on data associated with a cache using a second controller coupled to the first controller and coupled to a first memory; and storing the data on a second memory coupled to one of the first controller or the second controller.

公开(公告)号：US11467834B2

公开(公告)日：2022-10-11

申请号：US16914129

申请日：2020-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Andrew Chang

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/08 ,  G06F13/42 ,  G06F13/16 ,  G06F12/0817

Abstract: A system for computing. In some embodiments, the system includes: a memory, the memory including one or more function-in-memory circuits; and a cache coherent protocol interface circuit having a first interface and a second interface. A function-in-memory circuit of the one or more function-in-memory circuits may be configured to perform an operation on operands including a first operand retrieved from the memory, to form a result. The first interface of the cache coherent protocol interface circuit may be connected to the memory, and the second interface of the cache coherent protocol interface circuit may be configured as a cache coherent protocol interface on a bus interface.

公开(公告)号：US20220300426A1

公开(公告)日：2022-09-22

申请号：US17833219

申请日：2022-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Hongzhong Zheng

IPC: G06F12/0866

Abstract: According to some embodiments of the present invention, there is provided a hybrid cache memory for a processing device having a host processor, the hybrid cache memory comprising: a high bandwidth memory (HBM) configured to store host data; a non-volatile memory (NVM) physically integrated with the HBM in a same package and configured to store a copy of the host data at the HBM; and a cache controller configured to be in bi-directional communication with the host processor, and to manage data transfer between the HBM and NVM and, in response to a command received from the host processor, to manage data transfer between the hybrid cache memory and the host processor.

公开(公告)号：US11436165B2

公开(公告)日：2022-09-06

申请号：US16569657

申请日：2019-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F13/36 ,  G06F13/16 ,  G06F12/06

Abstract: A high-bandwidth memory (HBM) includes a memory and a controller. The controller receives a data write request from a processor external to the HBM and the controller stores an entry in the memory indicating at least one address of data of the data write request and generates an indication that a data bus is available for an operation during a cycle time of the data write request based on the data write request comprising sparse data or data-value similarity. Sparse data includes a predetermined percentage of data values equal to zero, and data-value similarity includes a predetermined amount of spatial value locality of the data values. The predetermined percentage of data values equal to zero of sparse data and the predetermined amount of spatial value locality of the special-value pattern are both based on a predetermined data granularity.

公开(公告)号：US11281554B2

公开(公告)日：2022-03-22

申请号：US16914119

申请日：2020-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Wenqin Huangfu

IPC: G06F11/30 ,  G06F11/34

Abstract: A method for computing. In some embodiments, the method includes: calculating an advantage score of a first computing task, the advantage score being a measure of an extent to which a plurality of function in memory circuits is capable of executing the first computing task more efficiently by than one or more extra-memory processing circuits, the first computing task including instructions and data; in response to determining that the advantage score of the first computing task is less than a first threshold, executing the first computing task by the one or more extra-memory processing circuits; and in response to determining that the first computing task is at least equal to the first threshold: compiling the instructions for execution by the function in memory circuits; formatting the data for the function in memory circuits; and executing the first computing task, by the function in memory circuits.

公开(公告)号：US20210374056A1

公开(公告)日：2021-12-02

申请号：US17246448

申请日：2021-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Andrew Chang ,  Ehsan Najafabadi

IPC: G06F12/06 ,  G06F12/0891 ,  G06F13/16 ,  G06F13/42 ,  G06F9/30 ,  G06F9/445

Abstract: Provided are systems, methods, and apparatuses for providing a storage resource. The method can include: operating a first controller coupled to a network interface in accordance with a cache coherent protocol; performing at least one operation on data associated with a cache using a second controller coupled to the first controller and coupled to a first memory; and storing the data on a second memory coupled to one of the first controller or the second controller.

公开(公告)号：US20210373951A1

公开(公告)日：2021-12-02

申请号：US17135901

申请日：2020-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Andrew Chang ,  Ehsan Najafabadi ,  Yasser A. Zaghloul

IPC: G06F9/50 ,  G06F13/40 ,  G06F13/42 ,  G06F13/16

Abstract: Provided are systems, methods, and apparatuses for resource allocation. The method can include: determining a first value of a parameter associated with at least one first device in a first cluster; determining a threshold based on the first value of the parameter; receiving a request for processing a workload at the first device; determining that a second value of the parameter associated with at least one second device in a second cluster meets the threshold; and responsive to meeting the threshold, routing at least a portion of the workload to the second device.