公开(公告)号：US11437377B2

公开(公告)日：2022-09-06

申请号：US17030841

申请日：2020-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Cheol Shin ,  Myung Gil Kang ,  Sadaaki Masuoka ,  Sang Hoon Lee ,  Sung Man Whang

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/04 ,  H01L21/02 ,  H01L29/16 ,  H01L21/8238

Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.

公开(公告)号：US11329039B2

公开(公告)日：2022-05-10

申请号：US16842053

申请日：2020-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon Baek ,  Myung Gil Kang ,  Jae-Ho Park ,  Seung Young Lee

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/118

Abstract: An integrated circuit includes first and second active regions, first and second standard cells on the first active region and the second active region, and a filler cell between the first and second standard cells and including first and second insulating isolations. The filler cell has a one-pitch dimension. The first and second insulating isolations are spaced the one-pitch dimension apart from each other. The first insulating isolation of the filler cell is disposed at a first boundary between the first standard cell and the filler cell. The second insulating isolation of the filler cell is disposed at a second boundary between the second standard cell and the filler cell. The first and second insulating isolations separate at least a part of the first active region, and at least a part of the second active region.

公开(公告)号：US10312156B2

公开(公告)日：2019-06-04

申请号：US15838665

申请日：2017-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo Yeon Jeong ,  Myung Gil Kang

IPC: H01L29/66 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/49 ,  H01L29/78

Abstract: A vertical fin field effect transistor (V-FinFET) is provided as follows. A substrate has a lower source/drain (S/D). A fin structure extends vertically from an upper surface of the lower S/D. The fin structure includes a sidewall having an upper sidewall portion, a lower sidewall portion and a center sidewall portion positioned therebetween. An upper S/D is disposed on an upper surface of the fin structure. An upper spacer is disposed on the upper sidewall portion. A lower spacer is disposed on the lower sidewall portion. A stacked structure including a gate oxide layer and a first gate electrode is disposed on an upper surface of the lower spacer, the center sidewall portion and a lower surface of the upper spacer. A second gate electrode is disposed on the first gate electrode.

公开(公告)号：US20160087026A1

公开(公告)日：2016-03-24

申请号：US14718685

申请日：2015-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Dongwon Kim ,  Ilryong Kim ,  Changwoo Oh ,  Keun Hwi Cho ,  Toshinori Fukai

IPC: H01L49/02 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L27/0629

Abstract: Embodiments of the inventive concepts provide a resistor and a semiconductor device including the same. The resistor includes a substrate, a device isolation layer in the substrate which defines active regions arranged in a first direction a resistance layer including resistance patterns that vertically protrude from the active regions and are connected to each other in the first direction, and contact electrodes on the resistance layer.

Abstract translation: 本发明构思的实施例提供一种电阻器和包括该电阻器的半导体器件。 电阻器包括衬底，衬底中的器件隔离层，其限定在第一方向上布置的有源区，包括从有源区垂直突出并在第一方向上彼此连接的电阻图案的电阻层，以及接触电极 电阻层。