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    Semiconductor devices
    1.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US12132101B2

    公开(公告)日：2024-10-29

    申请号：US17568170

    申请日：2022-01-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Beomjin Park ,  Dongwon Kim ,  Bongseok Suh ,  Daewon Kim

    IPC: H01L29/66 ,  H01L29/10 ,  H01L29/417 ,  H01L29/78

    CPC classification number: H01L29/6681 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/7851

    Abstract: A semiconductor device includes a first and second active regions extending in a first direction and having respective first and second widths in a second direction, the second width greater than the first width, a connection region connected to the first and second active regions and having a third width, between the first and second widths in the second direction, first and second gate structures respectively intersecting the first and second active regions and extending in the second direction, and a dummy structure intersecting at least a portion of the connection region, extending in the second direction, and between the first and second gate structures in the first direction. The dummy structure includes first and second pattern portions spaced apart from a side surface of the first gate structure by respective first and second distances in the first direction, the second distance greater than the first distance.

    INTEGRATED CIRCUIT DEVICE INCLUDING MULTI-CHANNEL TRANSISTOR
    2.
    发明公开
    INTEGRATED CIRCUIT DEVICE INCLUDING MULTI-CHANNEL TRANSISTOR 审中-公开

    公开(公告)号：US20240096955A1

    公开(公告)日：2024-03-21

    申请号：US18367852

    申请日：2023-09-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myunggil KANG ,  Beomjin Park ,  Dongwon Kim

    IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

    CPC classification number: H01L29/0673 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

    Abstract: In some embodiments, an integrated circuit device includes a substrate, a fin-type active region on the substrate that extends in a first direction, a plurality of semiconductor patterns spaced apart from an upper surface of the fin-type active region and include a channel region, a gate electrode, and a gate cut insulating pattern. The gate electrode extends in a second direction on the fin-type active region and is disposed between the plurality of semiconductor patterns. The gate electrode includes a first sidewall extending in the second direction and a second sidewall extending in the first direction. The gate cut insulating pattern is on a second sidewall of the gate electrode. An upper portion of the gate cut insulating pattern is wider in the second direction than a lower portion of the gate cut insulating pattern. A portion of a sidewall of the gate cut insulating pattern is curved.

    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
    4.
    发明申请
    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20230131215A1

    公开(公告)日：2023-04-27

    申请号：US17863741

    申请日：2022-07-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Keunhwi Cho ,  Jinkyu Kim ,  Myunggil Kang ,  Dongwon Kim ,  Kisung Suh

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78

    Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor structure extending from a substrate in a first direction and having first and second regions; forming a sacrificial gate pattern intersecting the first region of the semiconductor structure and extending in a second direction perpendicular to the first direction; reducing a width in the second direction of the second region of the semiconductor structure exposed to at least one side of the sacrificial gate pattern; forming at least one recess portion by removing a portion of the second region of the semiconductor structure; forming one or more source/drain regions in the recess portion of the semiconductor structure on at least one side of the sacrificial gate pattern; forming at least one gap region by removing the sacrificial gate pattern; and forming a gate structure by depositing a gate dielectric layer and a gate electrode in the gap region.

    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权

    公开(公告)号：US20230049858A1

    公开(公告)日：2023-02-16

    申请号：US17720741

    申请日：2022-04-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myung Gil Kang ,  Dongwon Kim ,  Keun Hwi Cho ,  Daewon Ha

    IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

    Abstract: A semiconductor device may include: an active pattern on a substrate and extending in a first direction; a plurality of source/drain patterns on the active pattern and spaced apart from each other in the first direction; a gate electrode between the plurality of source/drain patterns that crosses the active pattern and extends in a second direction intersecting the first direction; and a plurality of channel patterns stacked on the active pattern and configured to connect two or more of the source/drain patterns to each other. The channel patterns may be spaced apart from each other. Each of the channel patterns may include a first portion between the gate electrode and the source/drain patterns, and a plurality of second portions connected to the first portion and overlapped with the gate electrode in a direction perpendicular to a plane defined by an upper surface of the substrate.

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240405073A1

    公开(公告)日：2024-12-05

    申请号：US18538290

    申请日：2023-12-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyumin Yoo ,  Myung Gil Kang ,  Dongwon Kim ,  Jongsu Kim ,  Changwoo Noh ,  Beomjin Park ,  Soojin Jeong ,  Woosuk Choi

    IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

    Abstract: A semiconductor device is provided including an active pattern disposed on a substrate, a source/drain pattern on the active pattern, a channel pattern configured to electrically connect the source/drain patterns and including stacked semiconductor patterns spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, a gate pattern configured to cross between the source/drain patterns in a second direction parallel to the upper surface of the substrate, on the channel pattern, and to have a main gate portion and sub-gate portions, and inner gate spacers between the sub-gate portions and the source/drain pattern. A first distance between adjacent source/drain patterns along a given one of the sub-gate portions in the second direction is greater than a second distance between adjacent source/drain patterns passing through the semiconductor patterns in the second direction.

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