公开(公告)号：US08003480B2

公开(公告)日：2011-08-23

申请号：US12700796

申请日：2010-02-05

Applicant: Shin Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Shin Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/20

CPC classification number: H01L27/10852 ,  H01L28/91

Abstract: A process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM is disclosed. First, form a stacked structure. Second, form a photoresist layer on an upper oxide layer and then etch them. Third, deposit a polysilicon layer onto the upper oxide layer and the nitride layer. Fourth, deposit a nitrogen oxide layer on the polysilicon layer and the upper oxide layer. Sixth, partially etch the nitrogen oxide layer, the polysilicon layer and the upper oxide layer to form a plurality of vias. Seventh, oxidize the polysilicon layer to form a plurality of silicon dioxides surround the vias. Eighth, etch the nitride layer, the dielectric layer and the lower oxide layer beneath the vias. Ninth, form a metal plate and a capacitor lower electrode in each of the vias. Tenth, etch the nitrogen oxide layer, the polysilicon layer, the nitride layer and the dielectric layer.

Abstract translation: 公开了一种使用氧化物载体制造微米堆叠DRAM的电容器下电极的方法。 首先，形成堆叠结构。 其次，在上部氧化物层上形成光致抗蚀剂层，然后蚀刻它们。 第三，将多晶硅层沉积到上氧化物层和氮化物层上。 第四，在多晶硅层和上部氧化物层上沉积氮氧化物层。 第六，部分地蚀刻氮氧化物层，多晶硅层和上部氧化物层以形成多个通孔。 第七，氧化多晶硅层以形成围绕通孔的多个二氧化硅。 第八，在通孔下方蚀刻氮化物层，介电层和低氧化物层。 第九，在每个通孔中形成金属板和电容器下电极。 第十，蚀刻氮氧化物层，多晶硅层，氮化物层和电介质层。

公开(公告)号：US07781279B2

公开(公告)日：2010-08-24

申请号：US12018209

申请日：2008-01-23

Applicant: Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/8238

CPC classification number: H01L27/11521

Abstract: A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region, forming a floating gate dielectric layer on the exposed substrate and forming a floating gate layer adjacent to the dielectric sidewalls and on the floating gate dielectric layer.

Abstract translation: 一种用于制造存储器的方法，包括首先提供具有水平相邻的控制栅极区域和浮置栅极区域的衬底，该栅极区域包括牺牲层和牺牲侧壁，去除牺牲层和牺牲侧壁以露出衬底，形成邻近控制的电介质侧壁 栅极区域，在暴露的衬底上形成浮栅电介质层，并形成与电介质侧壁相邻的浮栅极和浮置栅极电介质层。

公开(公告)号：US07700991B2

公开(公告)日：2010-04-20

申请号：US11946868

申请日：2007-11-29

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

IPC: H01L29/76

CPC classification number: H01L29/7881 ,  H01L29/66825

Abstract: A method for fabricating the memory structure includes: providing a substrate having a pad, forming an opening in the pad, forming a first spacer on a sidewall of the opening, filling the opening with a sacrificial layer, removing the first spacer and exposing a portion of the substrate, removing the exposed substrate to define a first trench and a second trench, removing the sacrificial layer to expose a surface of the substrate to function as a channel region, forming a first dielectric layer on a surface of the first trench, a surface of the second trench and a surface of the channel region, filling the first trench and the second trench with a first conductive layer, forming a second dielectric layer on a surface of the first conductive layer and the surface of the channel region, filling the opening with a second conductive layer, and removing the pad.

Abstract translation: 一种用于制造存储器结构的方法包括：提供具有焊盘的衬底，在焊盘中形成开口，在开口的侧壁上形成第一间隔物，用牺牲层填充开口，移除第一间隔物并露出一部分 去除所述暴露的衬底以限定第一沟槽和第二沟槽，去除所述牺牲层以暴露所述衬底的表面以用作沟道区域，在所述第一沟槽的表面上形成第一介电层， 第二沟槽的表面和沟道区的表面，用第一导电层填充第一沟槽和第二沟槽，在第一导电层的表面和沟道区的表面上形成第二介电层，填充第二沟槽 用第二导电层打开，并移除垫。

公开(公告)号：US20090127610A1

公开(公告)日：2009-05-21

申请号：US12101164

申请日：2008-04-11

Applicant: Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L29/00 ,  H01L21/336

CPC classification number: H01L27/115 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: A non-volatile memory disposed on a substrate includes active regions, a memory array, and contacts. The active regions defined by isolation structures disposed in the substrate are extended in a first direction. The memory array is disposed on the substrate and includes memory cell columns, control gate lines and select gate lines. Each of the memory cell columns includes memory cells connected to one another in series and a source/drain region disposed in the substrate outside the memory cells. The contacts are disposed on the substrate at a side of the memory array and arranged along a second direction. The second direction crosses over the first direction. Each of the contacts extends across the isolation structures and connects the source/drain regions in the substrate at every two of the adjacent active regions.

Abstract translation: 设置在基板上的非易失性存储器包括有源区，存储器阵列和触点。 由设置在基板中的隔离结构限定的有源区域沿第一方向延伸。 存储器阵列设置在衬底上，并且包括存储单元列，控制栅极线和选择栅极线。 每个存储单元列包括彼此串联的存储单元和设置在存储单元外部的衬底中的源/漏区。 触点在存储器阵列的一侧设置在衬底上，并沿第二方向布置。 第二个方向穿过第一个方向。 每个触点延伸穿过隔离结构，并且在每个相邻的活性区域的每两个处连接衬底中的源极/漏极区域。

公开(公告)号：US20090047765A1

公开(公告)日：2009-02-19

申请号：US11955393

申请日：2007-12-13

Applicant: Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A method of manufacturing a non-volatile memory is provided. In the method, a first dielectric layer, a first conductive layer, and a first cap layer are formed sequentially on a substrate. The first cap layer and the first conductive layer are patterned to form first gate structures. A second dielectric layer is formed on the sidewall of the first gate structures, and a portion of the first dielectric layer is removed to expose the substrate between the first gate structures. An epitaxy layer is formed on the substrate between two first gate structures. A third dielectric layer is formed on the epitaxy layer. A second conductive layer is formed on the third dielectric layer. The first cap layer and a portion of the first conductive layer are removed to form second gate structures. Finally, a doped region is formed in the substrate at two sides of the second gate structures.

Abstract translation: 提供一种制造非易失性存储器的方法。 在该方法中，在基板上依次形成第一介电层，第一导电层和第一盖层。 图案化第一盖层和第一导电层以形成第一栅极结构。 在第一栅极结构的侧壁上形成第二介电层，并且去除第一介电层的一部分以在第一栅极结构之间露出衬底。 在两个第一栅极结构之间的衬底上形成外延层。 在外延层上形成第三介电层。 在第三电介质层上形成第二导电层。 去除第一盖层和第一导电层的一部分以形成第二栅极结构。 最后，在第二栅极结构的两侧在衬底中形成掺杂区域。

公开(公告)号：US20090040823A1

公开(公告)日：2009-02-12

申请号：US11946872

申请日：2007-11-29

Applicant: Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: G11C16/04

CPC classification number: H01L27/115 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11524

Abstract: A flash memory is provided. A sawtooth gate conductor line, which interconnects the select gates of the select gate transistors arranged on the same column is provided. The sawtooth gate conductor line, which is disposed on both distal ends of a memory cell string, increases the integration of the flash memory. The sawtooth gate conductor line results in select gate transistors having different select gate lengths and produces at least one depletion-mode select transistor at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on.

Abstract translation: 提供闪存。 提供了将布置在同一列上的选择栅极晶体管的选通栅极互连的锯齿波导线。 设置在存储单元串的两个远端上的锯齿形栅极导线增加了闪速存储器的集成。 锯齿波导线导致选择栅极晶体管具有不同的选择栅极长度，并在存储单元串的一侧产生至少一个耗尽型选择晶体管。 耗尽模式的选择栅晶体管总是导通。

公开(公告)号：US20090032860A1

公开(公告)日：2009-02-05

申请号：US11960720

申请日：2007-12-20

Applicant: Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang ,  Hsi-Hua Chang

Inventor： Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang ,  Hsi-Hua Chang

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/66825 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7883

Abstract: A programmable memory structure includes a substrate, an active area, a common-source and a common-drain respectively disposed on each side of the active area, a first and a second source contact electrically connected to the common-source, a first and a second drain contact electrically connected to the common-drain, and between the first and the second source contact and the first and the second drain contact a plurality of programmable memory cells including a first and a second dielectric layer respectively encapsulating a first and a second floating gate.

Abstract translation: 可编程存储器结构包括分别设置在有源区的每一侧上的衬底，有源区，公共源和公共漏极，电连接到共源的第一和第二源极触点，第一和 第二漏极接触电连接到共漏极，并且在第一和第二源极接触之间以及第一和第二漏极接触之间，多个可编程存储器单元包括分别封装第一和第二浮置的第一和第二介电层 门。

公开(公告)号：US07482227B1

公开(公告)日：2009-01-27

申请号：US11863282

申请日：2007-09-28

Applicant: Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/8247

CPC classification number: H01L27/11521

Abstract: A method for manufacturing a flash memory includes providing a substrate with a sacrificial oxide layer, a sacrificial poly-Si layer, a hard mask layer and a trench exposing part of the substrate and filled with an oxide layer, later depositing a oxide layer conformally on the sacrificial oxide layer and the oxide layer, and afterwards removing the oxide layer on the sacrificial oxide layer and on the top of the oxide layer and the sacrificial oxide layer to form a spacer as a STI oxide spacer.

Abstract translation: 一种用于制造闪速存储器的方法包括：提供具有牺牲氧化物层，牺牲多晶硅层，硬掩模层和暴露衬底部分的衬底并填充氧化物层的衬底，然后将氧化物层保形地 牺牲氧化物层和氧化物层，然后去除牺牲氧化物层上和氧化物层和牺牲氧化物层的顶部上的氧化物层，以形成作为STI氧化物间隔物的间隔物。

公开(公告)号：US20090014886A1

公开(公告)日：2009-01-15

申请号：US11951274

申请日：2007-12-05

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

IPC: H01L23/522 ,  H01L21/768 ,  H02H9/00

CPC classification number: H01L27/0251 ,  H01L27/10894

Abstract: The invention provides a dynamic random access memory (DRAM) with an electrostatic discharge (ESD) region. The upper portion of the ESD plug is metal, and the lower portion of the ESD plug is polysilicon. This structure may improve the mechanical strength of the ESD region and enhance thermal conductivity from electrostatic discharging. In addition, the contact area between the ESD plugs and the substrate can be reduced without increasing aspect ratio of the ESD plugs. The described structure is completed by a low critical dimension controlled patterned photoresist, such that the processes and equipments are substantially maintained without changing by a wide margin.

Abstract translation: 本发明提供一种具有静电放电（ESD）区域的动态随机存取存储器（DRAM）。 ESD插头的上部是金属，ESD插头的下部是多晶硅。 该结构可以提高ESD区域的机械强度并增强静电放电的导热性。 此外，可以减少ESD插头和基板之间的接触面积，而不增加ESD插头的纵横比。 所描述的结构由低临界尺寸控制的图案化光致抗蚀剂完成，使得工艺和设备基本上保持而不会大幅变化。

公开(公告)号：US20090011557A1

公开(公告)日：2009-01-08

申请号：US11863282

申请日：2007-09-28

Applicant: Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/336

CPC classification number: H01L27/11521

Abstract: A method for manufacturing a flash memory includes providing a substrate with a sacrificial oxide layer, a sacrificial poly-Si layer, a hard mask layer and a trench exposing part of the substrate and filled with an oxide layer, later depositing a oxide layer conformally on the sacrificial oxide layer and the oxide layer, and afterwards removing the oxide layer on the sacrificial oxide layer and on the top of the oxide layer and the sacrificial oxide layer to form a spacer as a STI oxide spacer.

Abstract translation: 一种用于制造闪速存储器的方法包括：提供具有牺牲氧化物层，牺牲多晶硅层，硬掩模层和暴露衬底部分的衬底并填充氧化物层的衬底，然后将氧化物层保形地 牺牲氧化物层和氧化物层，然后去除牺牲氧化物层上和氧化物层和牺牲氧化物层的顶部上的氧化物层，以形成作为STI氧化物间隔物的间隔物。