公开(公告)号：US08330198B2

公开(公告)日：2012-12-11

申请号：US12758252

申请日：2010-04-12

申请人： Shin Bin Huang ,  Chung-Lin Huang ,  Ching-Nan Hsiao ,  Tzung Han Lee

发明人： Shin Bin Huang ,  Chung-Lin Huang ,  Ching-Nan Hsiao ,  Tzung Han Lee

IPC分类号： H01L27/108

CPC分类号： H01L27/0259

摘要： A device for preventing current-leakage is located between a transistor and a capacitor of a memory cell. The two terminals of the device for preventing current-leakage are respectively connected with a slave terminal of the transistor and an electric pole of the capacitor. The device for preventing current-leakage has at least two p-n junctions. The device for preventing current-leakage is a lateral silicon controlled rectifier, a diode for alternating current, or a silicon controlled rectifier. By utilizing the driving characteristic of the device for preventing current-leakage, electric charge stored in the capacitor hardly passes through the device for preventing current-leakage when the transistor is turned off to improve the current-leakage problem.

摘要翻译： 用于防止漏电的装置位于存储单元的晶体管和电容器之间。 用于防止漏电的装置的两个端子分别与晶体管的从端和电容器的电极连接。 用于防止漏电的装置具有至少两个p-n结。 用于防止漏电的装置是侧向可控硅整流器，用于交流电流的二极管或可控硅整流器。 通过利用用于防止漏电的装置的驱动特性，存储在电容器中的电荷几乎不会通过用于防止晶体管截止时漏电的装置，从而改善漏电问题。

公开(公告)号：US20090032858A1

公开(公告)日：2009-02-05

申请号：US11927616

申请日：2007-10-29

申请人： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

发明人： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A flash memory is provided. The flash memory features of having the select gate transistors to include two different channel structures, which are a recessed channel structure and a horizontal channel. Because of the design of the recessed channel structure, the space between the gate conductor lines, which are for interconnecting the select gates of the select gate transistors arranged on the same column, can be shortened. Therefore, the integration of the flash memory can be increased; and the process window of the STI process can be increased as well. In addition, at least one depletion-mode select gate transistor is at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on.

摘要翻译： 提供闪存。 具有选择栅极晶体管的闪存特征包括两个不同的沟道结构，它们是凹陷沟道结构和水平沟道。 由于凹陷沟道结构的设计，可以缩短用于互连布置在同一列上的选择栅极晶体管的选择栅极的栅极导体线之间的空间。 因此，可以增加闪存的集成; 并且可以增加STI过程的处理窗口。 此外，至少一个耗尽型选择栅极晶体管位于存储单元串的一侧。 耗尽模式的选择栅晶体管总是导通。

公开(公告)号：US07868377B2

公开(公告)日：2011-01-11

申请号：US11927616

申请日：2007-10-29

申请人： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

发明人： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC分类号： H01L29/94

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A flash memory is provided. The flash memory features of having the select gate transistors to include two different channel structures, which are a recessed channel structure and a horizontal channel. Because of the design of the recessed channel structure, the space between the gate conductor lines, which are for interconnecting the select gates of the select gate transistors arranged on the same column, can be shortened. Therefore, the integration of the flash memory can be increased; and the process window of the STI process can be increased as well. In addition, at least one depletion-mode select gate transistor is at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on.

摘要翻译： 提供闪存。 具有选择栅极晶体管的闪存特征包括两个不同的沟道结构，它们是凹陷沟道结构和水平沟道。 由于凹陷沟道结构的设计，可以缩短用于互连布置在同一列上的选择栅晶体管的选通栅极的栅极导体线之间的空间。 因此，可以增加闪存的集成; 并且可以增加STI过程的处理窗口。 此外，至少一个耗尽型选择栅极晶体管位于存储单元串的一侧。 耗尽模式的选择栅晶体管总是导通。

公开(公告)号：US08003480B2

公开(公告)日：2011-08-23

申请号：US12700796

申请日：2010-02-05

申请人： Shin Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

发明人： Shin Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC分类号： H01L21/20

CPC分类号： H01L27/10852 ,  H01L28/91

摘要： A process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM is disclosed. First, form a stacked structure. Second, form a photoresist layer on an upper oxide layer and then etch them. Third, deposit a polysilicon layer onto the upper oxide layer and the nitride layer. Fourth, deposit a nitrogen oxide layer on the polysilicon layer and the upper oxide layer. Sixth, partially etch the nitrogen oxide layer, the polysilicon layer and the upper oxide layer to form a plurality of vias. Seventh, oxidize the polysilicon layer to form a plurality of silicon dioxides surround the vias. Eighth, etch the nitride layer, the dielectric layer and the lower oxide layer beneath the vias. Ninth, form a metal plate and a capacitor lower electrode in each of the vias. Tenth, etch the nitrogen oxide layer, the polysilicon layer, the nitride layer and the dielectric layer.

摘要翻译： 公开了一种使用氧化物载体制造微米堆叠DRAM的电容器下电极的方法。 首先，形成堆叠结构。 其次，在上部氧化物层上形成光致抗蚀剂层，然后蚀刻它们。 第三，将多晶硅层沉积到上氧化物层和氮化物层上。 第四，在多晶硅层和上部氧化物层上沉积氮氧化物层。 第六，部分地蚀刻氮氧化物层，多晶硅层和上部氧化物层以形成多个通孔。 第七，氧化多晶硅层以形成围绕通孔的多个二氧化硅。 第八，在通孔下方蚀刻氮化物层，介电层和低氧化物层。 第九，在每个通孔中形成金属板和电容器下电极。 第十，蚀刻氮氧化物层，多晶硅层，氮化物层和电介质层。

公开(公告)号：US20090040823A1

公开(公告)日：2009-02-12

申请号：US11946872

申请日：2007-11-29

申请人： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

发明人： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC分类号： G11C16/04

CPC分类号： H01L27/115 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11524

摘要： A flash memory is provided. A sawtooth gate conductor line, which interconnects the select gates of the select gate transistors arranged on the same column is provided. The sawtooth gate conductor line, which is disposed on both distal ends of a memory cell string, increases the integration of the flash memory. The sawtooth gate conductor line results in select gate transistors having different select gate lengths and produces at least one depletion-mode select transistor at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on.

摘要翻译： 提供闪存。 提供了将布置在同一列上的选择栅极晶体管的选通栅极互连的锯齿波导线。 设置在存储单元串的两个远端上的锯齿形栅极导线增加了闪速存储器的集成。 锯齿波导线导致选择栅极晶体管具有不同的选择栅极长度，并在存储单元串的一侧产生至少一个耗尽型选择晶体管。 耗尽模式的选择栅晶体管总是导通。

公开(公告)号：US08148766B2

公开(公告)日：2012-04-03

申请号：US12244295

申请日：2008-10-02

申请人： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

发明人： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/3185 ,  H01L29/42324 ,  H01L29/66825

摘要： A nonvolatile memory cell is provided. A semiconductor substrate is provided. A conducting layer and a spacer layer are sequentially disposed above the semiconductor substrate. At least a trench having a bottom and plural side surfaces is defined in the conducting layer and the spacer layer. A first oxide layer is formed at the bottom of the trench. A dielectric layer is formed on the first oxide layer, the spacer layer and the plural side surfaces of the trench. A first polysilicon layer is formed in the trench. And a first portion of the dielectric layer on the spacer layer is removed, so that a basic structure for the nonvolatile memory cell is formed.

摘要翻译： 提供非易失性存储单元。 提供半导体衬底。 导电层和间隔层顺序地设置在半导体衬底之上。 在导电层和间隔层中限定具有底部和多个侧表面的至少一个沟槽。 第一氧化物层形成在沟槽的底部。 在第一氧化物层，间隔层和沟槽的多个侧表面上形成介电层。 在沟槽中形成第一多晶硅层。 并且去除间隔层上的电介质层的第一部分，从而形成用于非易失性存储单元的基本结构。

公开(公告)号：US20100013062A1

公开(公告)日：2010-01-21

申请号：US12244295

申请日：2008-10-02

申请人： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

发明人： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC分类号： H01L23/58 ,  H01L21/31

CPC分类号： H01L27/11521 ,  H01L21/3185 ,  H01L29/42324 ,  H01L29/66825

摘要： A nonvolatile memory cell is provided. A semiconductor substrate is provided. A conducting layer and a spacer layer are sequentially disposed above the semiconductor substrate. At least a trench having a bottom and plural side surfaces is defined in the conducting layer and the spacer layer. A first oxide layer is formed at the bottom of the trench. A dielectric layer is formed on the first oxide layer, the spacer layer and the plural side surfaces of the trench. A first polysilicon layer is formed in the trench. And a first portion of the dielectric layer on the spacer layer is removed, so that a basic structure for the nonvolatile memory cell is formed.

摘要翻译： 提供非易失性存储单元。 提供半导体衬底。 导电层和间隔层顺序地设置在半导体衬底之上。 在导电层和间隔层中限定具有底部和多个侧表面的至少一个沟槽。 第一氧化物层形成在沟槽的底部。 在第一氧化物层，间隔层和沟槽的多个侧表面上形成介电层。 在沟槽中形成第一多晶硅层。 并且去除间隔层上的电介质层的第一部分，从而形成用于非易失性存储单元的基本结构。

公开(公告)号：US07981743B2

公开(公告)日：2011-07-19

申请号：US12039744

申请日：2008-02-29

申请人： Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang

发明人： Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC分类号： H01L21/336 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L29/7923 ,  H01L27/115 ,  H01L27/11568

摘要： The memory cell of the present invention has two independent storage regions embedded into two opposite sidewalls of the control gate respectively. In this way, the data storage can be more reliable. Other features of the present invention are that the thickness of the dielectric layers is different, and the two independent storage regions are formed on opposite bottom sides of the opening by the etching process and form a shape like a spacer. The advantage of the aforementioned method is that the fabricating process is simplified and the difficulty of self-alignment is reduced.

摘要翻译： 本发明的存储单元具有分别嵌入控制门的两个相对的侧壁中的两个独立的存储区域。 以这种方式，数据存储可以更可靠。 本发明的其他特征是电介质层的厚度不同，并且两个独立的存储区域通过蚀刻工艺形成在开口的相对的底侧上并形成像间隔物的形状。 上述方法的优点是简化了制造工艺，并且减少了自对准的难度。

公开(公告)号：US20100279472A1

公开(公告)日：2010-11-04

申请号：US12838495

申请日：2010-07-19

申请人： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

发明人： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC分类号： H01L21/8239

CPC分类号： H01L27/115 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： In a manufacturing method of a non-volatile memory, a substrate is provided, and strip-shaped isolation structures are formed in the substrate. A first memory array including memory cell columns is formed on the substrate. Each memory cell column includes memory cells connected in series with one another, a source/drain region disposed in the substrate outside the memory cells, select transistors disposed between the source/drain region and the memory cells, control gate lines extending across the memory cell columns and in a second direction, and first select gate lines respectively connecting the select transistors in the second direction in series. First contacts are formed on the substrate at a side of the first memory array and arranged along the second direction. Each first contact connects the source/drain regions in every two adjacent active regions.

摘要翻译： 在非易失性存储器的制造方法中，提供衬底，并且在衬底中形成条形隔离结构。 包括存储单元列的第一存储器阵列形成在衬底上。 每个存储单元列包括彼此串联连接的存储器单元，设置在存储单元外部的衬底中的源极/漏极区域，设置在源极/漏极区域和存储器单元之间的选择晶体管，跨过存储器单元延伸的控制栅极线 列和第二方向，并且首先选择分别连接第二方向上的选择晶体管的栅极线。 第一触点形成在第一存储器阵列的一侧的基板上，并沿第二方向布置。 每个第一接触件在每两个相邻有效区域中连接源极/漏极区域。

公开(公告)号：US07713820B2

公开(公告)日：2010-05-11

申请号：US11945199

申请日：2007-11-26

申请人： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

发明人： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC分类号： H01L21/336

CPC分类号： H01L29/7887 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： A method for manufacturing a non-volatile memory is provided. An isolation structure is formed in a trench formed in a substrate. A portion of the isolation structure is removed to form a recess. A first dielectric layer and a first conductive layer are formed sequentially on the substrate. Bar-shaped cap layers are formed on the substrate. The first conductive layer not covered by the bar-shaped cap layers is removed to form first gate structures. A second dielectric layer is formed on the sidewalls of the first gate structures. A third dielectric layer is formed on the substrate between the first gate structures. A second conductive layer is formed on the third dielectric layer. The bar-shaped cap layers and a portion of the first conductive layer are removed to form second gate structures. A doped region is formed in the substrate at two sides of each of the second gate structures.

摘要翻译： 提供一种用于制造非易失性存储器的方法。 在衬底中形成的沟槽中形成隔离结构。 去除隔离结构的一部分以形成凹部。 在基板上依次形成第一介电层和第一导电层。 在基板上形成棒状盖层。 未被棒状帽层覆盖的第一导电层被去除以形成第一栅极结构。 在第一栅极结构的侧壁上形成第二介电层。 在第一栅极结构之间的衬底上形成第三电介质层。 在第三电介质层上形成第二导电层。 条形盖层和第一导电层的一部分被去除以形成第二栅极结构。 在每个第二栅极结构的两侧在衬底中形成掺杂区域。