公开(公告)号：US20210328050A1

公开(公告)日：2021-10-21

申请号：US17362956

申请日：2021-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Chih-Tung Yeh

IPC: H01L29/778 ,  H01L29/66

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer, wherein the composition of the first III-V compound layer and the second III-V compound layer are different from each other. A source electrode and a drain electrode are disposed on the second III-V compound layer. A gate electrode is disposed on the second III-V compound layer between the source electrode and the drain electrode. An insulating layer is disposed between the drain electrode and the gate electrode and covering the second III-V compound layer. Numerous electrodes are disposed on the insulating layer and contact the insulating layer, wherein the electrodes are positioned between the gate electrode and the drain electrode and a distribution of the electrodes decreases along a direction toward the gate electrode.

公开(公告)号：US20210020768A1

公开(公告)日：2021-01-21

申请号：US16535052

申请日：2019-08-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Chih-Tung Yeh

IPC: H01L29/778 ,  H01L29/66

Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A source electrode and a drain electrode are disposed on the second III-V compound layer. The gate electrode is disposed on the second III-V compound layer between the source electrode and the drain electrode. An insulating layer is disposed between the drain electrode and the gate electrode and covers the second III-V compound layer. At least one electrode is disposed on the insulating layer and contacts the insulating layer, wherein a voltage is applied to the electrode.

公开(公告)号：US12262554B2

公开(公告)日：2025-03-25

申请号：US17543607

申请日：2021-12-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh

IPC: H10D64/01 ,  H01L21/225 ,  H10D30/47 ,  H10D62/13 ,  H10D62/85 ,  H10D64/23 ,  H10D64/62

Abstract: A semiconductor device includes a III-V compound semiconductor layer and a source/drain structure. The source/drain structure is disposed on the III-V compound semiconductor layer. The source/drain structure includes a metal layer and metal silicide patterns. The metal layer is disposed on the metal silicide patterns, and a portion of the metal layer is disposed between the metal silicide patterns adjacent to each other.

公开(公告)号：US20250015173A1

公开(公告)日：2025-01-09

申请号：US18888136

申请日：2024-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chuan Huang ,  Chih-Tung Yeh ,  Chun-Ming Chang ,  Bo-Rong Chen ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/778 ,  H01L21/265 ,  H01L21/28 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

公开(公告)号：US12100758B2

公开(公告)日：2024-09-24

申请号：US18370875

申请日：2023-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Chih-Tung Yeh

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/66462

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer, wherein the composition of the first III-V compound layer and the second III-V compound layer are different from each other. A source electrode and a drain electrode are disposed on the second III-V compound layer. A gate electrode is disposed on the second III-V compound layer between the source electrode and the drain electrode. An insulating layer is disposed between the drain electrode and the gate electrode and covering the second III-V compound layer. Numerous electrodes are disposed on the insulating layer and contact the insulating layer, wherein the electrodes are positioned between the gate electrode and the drain electrode and a distribution of the electrodes decreases along a direction toward the gate electrode.

公开(公告)号：US12057490B2

公开(公告)日：2024-08-06

申请号：US17500954

申请日：2021-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Ming-Chang Lu

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/778

Abstract: A high electron mobility transistor includes a substrate. A first III-V compound layer is disposed on the substrate. A second III-V compound layer is embedded within the first III-V compound layer. A P-type gallium nitride gate is embedded within the second III-V compound layer. A gate electrode is disposed on the second III-V compound layer and contacts the P-type gallium nitride gate. A source electrode is disposed at one side of the gate electrode. A drain electrode is disposed at another side of the gate electrode.

公开(公告)号：US20240014306A1

公开(公告)日：2024-01-11

申请号：US17886491

申请日：2022-08-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Ruey-Chyr Lee ,  Wen-Jung Liao

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/20 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L29/7786 ,  H01L29/205 ,  H01L29/2003 ,  H01L29/66462 ,  H01L21/30604 ,  H01L21/3065

Abstract: A semiconductor device provided with features of depletion mode (D-mode) and enhancement mode (E-mode) GaN devices, including a substrate with a first region and a second region defined thereon, a GaN channel layer on the substrate, a AlGaN layer on the GaN channel layer, a p-GaN layer on the AlGaN layer in the first region, a Al-based passivation layer on the AlGaN layer and p-GaN layer, and gate contact openings, wherein the gate contact opening on the first region extends through the Al-based passivation layer to the top surface of p-GaN layer, the gate contact opening on the second region extends through the Al-based passivation layer to the surface of AlGaN layer, and the surfaces of p-GaN layer and AlGaN layer are both flat surfaces without recess feature.

公开(公告)号：US20240006511A1

公开(公告)日：2024-01-04

申请号：US17876552

申请日：2022-07-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Wen-Jung Liao

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778 ,  H01L23/31

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/778 ,  H01L23/3171 ,  H01L23/3192

Abstract: A high-electron mobility transistor includes a substrate, a buffer layer over the substrate, a barrier layer over the buffer layer, and a gate structure on the barrier layer. The gate structure includes a cap layer and a gate over the cap layer. The cap layer includes a gate-leakage suppressing region on its sidewall.

公开(公告)号：US11791407B2

公开(公告)日：2023-10-17

申请号：US17330420

申请日：2021-05-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Chun-Liang Hou ,  Wen-Jung Liao ,  Ruey-Chyr Lee

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L29/205 ,  H01L29/45 ,  H01L29/20

CPC classification number: H01L29/7783 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/454 ,  H01L29/66462

Abstract: A semiconductor transistor structure with reduced contact resistance includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a two-dimensional electron gas (2DEG) layer at an interface between the barrier layer and the channel layer, and a recess in a contact region. The recess penetrates through the barrier layer and extends into the channel layer. An Ohmic contact metal is disposed in the recess. The Ohmic contact metal is in direct contact with a vertical side surface of the barrier layer in the recess and in direct contact with an inclined side surface of the 2DEG layer and the channel layer in the recess.

公开(公告)号：US20230231003A1

公开(公告)日：2023-07-20

申请号：US18123972

申请日：2023-03-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Kuang-Pi Lee ,  Wen-Jung Liao

IPC: H01L27/06

CPC classification number: H01L28/60 ,  H01L27/0629 ,  H01L27/0605

Abstract: A capacitor structure includes an insulation layer and a capacitor unit disposed on the insulation layer. The capacitor unit includes a first electrode, a second electrode, a first dielectric layer, and a patterned conductive layer. The second electrode is disposed above the first electrode in a vertical direction. The first dielectric layer is disposed between the first electrode and the second electrode in the vertical direction. The patterned conductive layer is disposed between first electrode and the second electrode, the patterned conductive layer is electrically connected with the first electrode, and the first dielectric layer surrounds the patterned conductive layer in a horizontal direction.