公开(公告)号：US10580883B2

公开(公告)日：2020-03-03

申请号：US15912526

申请日：2018-03-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Chih-Kai Kang

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L21/84

Abstract: A method of forming a fin forced stack inverter includes the following steps. A substrate including a first fin, a second fin and a third fin across a first active area along a first direction is provided, wherein the first fin, the second fin and the third fin are arranged side by side. A fin remove inside active process is performed to remove at least a part of the second fin in the first active area. A first gate is formed across the first fin and the third fin in the first active area along a second direction. The present invention also provides a 1-1 fin forced fin stack inverter formed by said method.

公开(公告)号：US20250072015A1

公开(公告)日：2025-02-27

申请号：US18370402

申请日：2023-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Yih Chen ,  Kuo-Hsing Lee ,  Chun-Hsien Lin ,  Kun-Szu Tseng ,  Sheng-Yuan Hsueh ,  Yao-Jhan Wang

IPC: H01L29/94 ,  H01L27/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region, forming a fin-shaped structure on the MOSCAP region, forming a shallow trench isolation (STI) around the substrate and the fin-shaped structure, performing a first etching process to remove part of the STI on the MOSCAP region, and then performing a second etching process to remove part of the STI on the non-MOSCAP region and the MOSCAP region.

公开(公告)号：US12206018B2

公开(公告)日：2025-01-21

申请号：US18614735

申请日：2024-03-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chien-Liang Wu ,  Kuo-Yu Liao

IPC: H01L29/778 ,  H01L27/06 ,  H01L29/06 ,  H01L29/20 ,  H01L29/66

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, forming a buffer layer on the substrate, forming a mesa isolation on the HEMT region, forming a HEMT on the mesa isolation, and then forming a capacitor on the capacitor region. Preferably, a bottom electrode of the capacitor contacts the buffer layer directly.

公开(公告)号：US12200947B2

公开(公告)日：2025-01-14

申请号：US18395762

申请日：2023-12-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ting-Hsiang Huang ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chih-Kai Kang

IPC: H10B61/00 ,  H10N50/10 ,  H10N50/80

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle and a top view of the first metal interconnection includes an ellipse overlapping the circle.

公开(公告)号：US20250014661A1

公开(公告)日：2025-01-09

申请号：US18890725

申请日：2024-09-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chi-Horn Pai ,  Chih-Kai Kang

IPC: G11C17/16 ,  H10B20/25

Abstract: A bit cell structure for one-time-programming is provided in the present invention, including a first doped region in a substrate and electrically connected to a source line, a second doped region in the substrate and provided with a source and a drain, wherein the drain is electrically connected with a bit line, a doped channel region in the substrate with a first part and a second part connecting respectively to the first doped region and the source of second doped region in a first direction, and a width of the first part in a second direction perpendicular to the first direction is less than a width of the second part and less than a width of the first doped region, and a word line traversing over the second doped region and between the source and drain.

公开(公告)号：US20240215264A1

公开(公告)日：2024-06-27

申请号：US18433347

申请日：2024-02-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh

IPC: H10B63/00 ,  H10B61/00 ,  H10N50/01 ,  H10N70/00

CPC classification number: H10B63/30 ,  H10B61/22 ,  H10B63/80 ,  H10N50/01 ,  H10N70/011

Abstract: The invention discloses a data storage cell. The data storage cell includes a storage structure, a first transistor, and a second transistor. A first end of the storage structure is electrically connected to a bit line. The first transistor includes a first gate, a first drain, and a first source. The second transistor includes a second gate, a second drain, and a second source. The first gate is electrically connected to the second gate. A second end of the storage structure is electrically connected to the first drain and the second drain. The first source and the second source are electrically connected to a source line.

公开(公告)号：US20240153812A1

公开(公告)日：2024-05-09

申请号：US18074511

申请日：2022-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Kai Lin ,  Chi-Horn Pai ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chih-Kai Kang

IPC: H01L21/762 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L21/762 ,  H01L21/76831 ,  H01L21/76897 ,  H01L29/66545

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a shallow trench isolation (STI) in a substrate, forming a first gate structure on the substrate and adjacent to the STI, forming a first doped region between the first gate structure and the STI, forming a second doped region between the first doped region and the first gate structure, forming a first contact plug on the first doped region, and then forming a second contact plug on the second doped region.

公开(公告)号：US20230275147A1

公开(公告)日：2023-08-31

申请号：US18144822

申请日：2023-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chien-Liang Wu ,  Kuo-Yu Liao

IPC: H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/778 ,  H01L27/0629 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/0649

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, forming a first mesa isolation on the HEMT region and a second mesa isolation on the capacitor region, forming a HEMT on the first mesa isolation, and then forming a capacitor on the second mesa isolation.

公开(公告)号：US20230275146A1

公开(公告)日：2023-08-31

申请号：US18144811

申请日：2023-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chien-Liang Wu ,  Kuo-Yu Liao

IPC: H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/778 ,  H01L27/0629 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/0649

Abstract: A semiconductor device includes a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, a first mesa isolation on the HEMT region, a HEMT on the first mesa isolation, a second mesa isolation on the capacitor region, and a capacitor on the second mesa isolation. The semiconductor device further includes buffer layer between the substrate, the first mesa isolation, and the second mesa isolation, in which bottom surfaces of the first mesa isolation and the second mesa isolation are coplanar.

公开(公告)号：US20230135847A1

公开(公告)日：2023-05-04

申请号：US18088761

申请日：2022-12-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Te-Wei Yeh ,  Chien-Liang Wu

IPC: H10B61/00 ,  G11C7/18 ,  H10N50/80

Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).