公开(公告)号：US20230261071A1

公开(公告)日：2023-08-17

申请号：US18132435

申请日：2023-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/423 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L29/4234 ,  H01L29/792 ,  H01L29/66833

Abstract: A semiconductor structure includes a substrate, an insulating layer disposed on the substrate, an active layer disposed on the insulating layer, a plurality of isolation structures in the active layer to define a first device region and a non-device region of the active layer, a first semiconductor device formed on the first device region of the active layer, and a charge trap structure extending through the non-device region of the active layer. In a plane view, the charge trap structure and the non-device region form concentric closed ring surrounding the first device region.

公开(公告)号：US20230240161A1

公开(公告)日：2023-07-27

申请号：US17673812

申请日：2022-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Chung-Yi Chiu

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1273 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/16 ,  H01L45/146 ,  H01L45/1233

Abstract: A semiconductor memory device includes a substrate and a transistor disposed on the substrate. The transistor includes a source doped region, a drain doped region, a channel region, and a gate over the channel region. A data storage region is in proximity to the transistor and recessed into the substrate. The data storage region includes a ridge and a V-shaped groove. A bottom electrode layer conformally covers the ridge and V-shaped groove within the data storage region. A resistive-switching layer conformally covers the bottom electrode layer. A top electrode layer covers the resistive-switching layer.

公开(公告)号：US20230085517A1

公开(公告)日：2023-03-16

申请号：US17988720

申请日：2022-11-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/20 ,  H01L29/205

Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from the composition of the second III-V compound layer. A third III-V compound layer is disposed on the second III-V compound layer. The first III-V compound layer and the third III-V compound layer are composed of the same group III-V elements. The third III-V compound layer includes a body and numerous finger parts. Each of the finger parts is connected to the body. All finger parts are parallel to each other and do not contact each other. A source electrode, a drain electrode and a gate electrode are disposed on the first III-V compound layer.

公开(公告)号：US20220246750A1

公开(公告)日：2022-08-04

申请号：US17207719

申请日：2021-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Hsun-Wen Wang

IPC: H01L29/778 ,  H01L29/66

Abstract: The present disclosure relates to a semiconductor device and its manufacturing method, and the semiconductor device includes a substrate, a channel layer, a gate electrode, a first electrode, a second electrode, and a metal plate. The channel layer is disposed on the substrate, and the gate electrode is disposed on the channel layer. The first electrode and the second electrode are disposed on the channel layer, at two opposite sides of the gate electrode respectively. The metal plate is disposed over the channel layer, between the first electrode and the gate electrode. The metal plate includes a first extending portion and a second extending portion, wherein the second extending portion extends towards the substrate without contacting the channel layer, and the first extending portion extends toward and directly contacts the first electrode or the second electrode.

公开(公告)号：US20220238694A1

公开(公告)日：2022-07-28

申请号：US17203723

申请日：2021-03-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Hsun-Wen Wang

IPC: H01L29/66 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer disposed on the substrate, a barrier layer disposed on the channel layer, a first passivation layer disposed on the barrier layer, a plurality of trenches through at least a portion of the first passivation layer, and a conductive plate structure disposed on the first passivation layer. The conductive plate structure includes a base portion over the trenches and a plurality of protruding portions extending from a lower surface of the base portion and into the trenches.

公开(公告)号：US20220157979A1

公开(公告)日：2022-05-19

申请号：US17148526

申请日：2021-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate capping layer, a dielectric layer, and a gate electrode. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate capping layer is disposed on the semiconductor barrier layer, and the dielectric layer conformally covers the gate capping layer and surrounds the periphery of the gate capping layer. The gate electrode is disposed on the dielectric layer and covers at least one sidewall of the gate capping layer.

公开(公告)号：US20220059762A1

公开(公告)日：2022-02-24

申请号：US17024680

申请日：2020-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L45/00

Abstract: A resistive memory device includes a first stacked structure and a second stacked structure. The first stacked structure includes a first bottom electrode, a first top electrode disposed on the first bottom electrode, and a first variable resistance layer disposed between the first bottom electrode and the first top electrode in a vertical direction. The second stacked structure includes a second bottom electrode, a second top electrode disposed on the second bottom electrode, and a second variable resistance layer disposed between the second bottom electrode and the second top electrode in the vertical direction. A thickness of the first variable resistance layer is less than a thickness of the second variable resistance layer for increasing the number of switchable resistance states of the resistive memory device.

公开(公告)号：US11165020B2

公开(公告)日：2021-11-02

申请号：US16655262

申请日：2019-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L45/00 ,  H01L27/24

Abstract: A multi-bit resistive random access memory cell includes a plurality of bottom electrodes, a plurality of dielectric layers, a top electrode and a resistance layer. The bottom electrodes and the dielectric layers are interleaved layers, each of the bottom electrodes is sandwiched by the dielectric layers, and a through hole penetrates through the interleaved layers. The top electrode is disposed in the through hole. The resistance layer is disposed on a sidewall of the through hole and is between the top electrode and the interleaved layers, thereby the top electrode, the resistance layer and the bottom electrodes constituting a multi-bit resistive random access memory cell. The present invention also provides a method of forming the multi-bit resistive random access memory cell.

公开(公告)号：US20210111340A1

公开(公告)日：2021-04-15

申请号：US16655262

申请日：2019-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L45/00 ,  H01L27/24

Abstract: A multi-bit resistive random access memory cell includes a plurality of bottom electrodes, a plurality of dielectric layers, a top electrode and a resistance layer. The bottom electrodes and the dielectric layers are interleaved layers, each of the bottom electrodes is sandwiched by the dielectric layers, and a through hole penetrates through the interleaved layers. The top electrode is disposed in the through hole. The resistance layer is disposed on a sidewall of the through hole and is between the top electrode and the interleaved layers, thereby the top electrode, the resistance layer and the bottom electrodes constituting a multi-bit resistive random access memory cell. The present invention also provides a method of forming the multi-bit resistive random access memory cell.

公开(公告)号：US20210098622A1

公开(公告)日：2021-04-01

申请号：US17118524

申请日：2020-12-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/033 ,  H01L21/324 ,  H01L21/225 ,  H01L21/306 ,  H01L29/10

Abstract: A method of forming a semiconductor structure is disclosed. First, a substrate is provided, including an upper surface. A gate structure is disposed on the upper surface. A spacer is disposed on a sidewall of the gate structure. A first region is located in the substrate. A second region is located in the substrate. The first region and the second region are dry etched to form a first trench and a second trench, respectively. The second region is masked. The first region is then wet etched through the first trench to form a widened first trench. A stress-inducing layer is then formed in the widened first trench and in the second trench.