Hardware-assisted memory disaggregation with recovery from network failures using non-volatile memory

    公开(公告)号:US11620192B2

    公开(公告)日:2023-04-04

    申请号:US16926520

    申请日:2020-07-10

    Applicant: VMware, Inc.

    Abstract: Techniques for implementing hardware-assisted memory disaggregation with recovery from network failures/problems are provided. In one set of embodiments, a hardware controller of a computer system can maintain a copy of a “remote memory” of the computer system (i.e., a section of the physical memory address space of the computer system that maps to a portion of the physical system memory of a remote computer system) in a local backup memory. The backup memory may be implemented using a non-volatile memory that is slower, but also less expensive, than conventional dynamic random-access memory (DRAM). Then, if the hardware controller is unable to retrieve data in the remote memory from the remote computer system within a specified time window due to, e.g., a network failure or other problem, the hardware controller can retrieve the data from the backup memory, thereby avoiding a hardware error condition (and potential application/system crash).

    Smart prefetching for remote memory

    公开(公告)号:US11586545B2

    公开(公告)日:2023-02-21

    申请号:US17367048

    申请日:2021-07-02

    Applicant: VMware, Inc.

    Abstract: Memory pages of a local application program are prefetched from a memory of a remote host. A method of prefetching the memory pages from the remote memory includes detecting that a cache-line access made by a processor executing the local application program is an access to a cache line containing page table data of the local application program, identifying data pages that are referenced by the page table data, and fetching the identified data pages from the remote memory and storing the fetched data pages in a local memory.

    OPTIMIZED MEMORY TIERING
    53.
    发明申请

    公开(公告)号:US20230033029A1

    公开(公告)日:2023-02-02

    申请号:US17382839

    申请日:2021-07-22

    Applicant: VMware, Inc.

    Abstract: Disclosed are various embodiments for optimized memory tiering. A first page can be allocated in a first memory for a process, the first memory being associated with a first memory tier. Accesses of the first page by the process during execution of the process can be monitored. Then, accesses of the first page by the process during execution of the process can be compared to an allocation policy to make a first determination to move the contents of the first page from the first memory to a second memory associated with a second memory tier. Next, the contents of the first page can be copied from the first memory to a second page in the second memory in response to the first determination.

    HIGH THROUGHPUT MEMORY PAGE RECLAMATION

    公开(公告)号:US20220398014A1

    公开(公告)日:2022-12-15

    申请号:US17344514

    申请日:2021-06-10

    Applicant: VMware, Inc.

    Abstract: Disclosed are various embodiments for high throughput reclamation of pages in memory. A first plurality of pages in a memory of the computing device are identified to reclaim. In addition, a second plurality of pages in the memory of the computing device are identified to reclaim. The first plurality of pages are prepared for storage on a swap device of the computing device. Then, a write request is submitted to a swap device to store the first plurality of pages. After submission of the write request, the second plurality of pages are prepared for storage on the swap device while the swap device completes the write request.

    Failure-atomic persistent memory logging using binary translation

    公开(公告)号:US10817389B2

    公开(公告)日:2020-10-27

    申请号:US16256567

    申请日:2019-01-24

    Applicant: VMware, Inc.

    Abstract: A module for rewriting application code as a failure-atomic transaction is disclosed. An application delineates a code fragment that is to become a failure-atomic transaction by writing a tx_begin( ) and tx_end( ) functions into its code. A module detects the tx_begin( ) and tx_end( ) functions and rewrites the code fragment as a failure-atomic transaction. The rewritten code is then available to be executed by the application. The rewritten code stores values and locations of stores to persistent memory locations so that the transaction can be either undone or redone in the case of an application error or a power failure. If the transaction is an undo type of transaction, the application can be rolled back to a state prior to the failure. If the transaction is a redo type of transaction, the application can be advanced to a correct state after the error.

    Micro-journal based transaction logging

    公开(公告)号:US10528436B2

    公开(公告)日:2020-01-07

    申请号:US15192940

    申请日:2016-06-24

    Applicant: VMware, Inc.

    Abstract: Techniques for using micro-journals to ensure crash consistency of a transactional application are provided. In one embodiment, a computer system can receive a transaction associated with the transactional application, where the transaction includes a plurality of modifications to data or metadata of the transactional application. The computer system can further select a free micro-journal from a pool of micro-journals, where the pool of micro-journals are stored in a byte-addressable persistent memory of the computer system, and where each micro-journal in the pool is configured to record journal entries for a single transaction at a time. The computer system can then write journal entries into the micro-journal corresponding to the plurality of modifications included in the transaction and commit the journal entries to the byte-addressable persistent memory.

    COMMIT COALESCING FOR MICRO-JOURNAL BASED TRANSACTION LOGGING

    公开(公告)号:US20200004735A1

    公开(公告)日:2020-01-02

    申请号:US16560951

    申请日:2019-09-04

    Applicant: VMware, Inc.

    Abstract: Techniques for using commit coalescing when performing micro-journal-based transaction logging are provided. In one embodiment a computer system can maintain, in a volatile memory, a globally ascending identifier, a first list of free micro-journals, and a second list of in-flight micro-journals. The computer system can further receive a transaction comprising a plurality of modifications to data or metadata stored in the byte-addressable persistent memory, select a micro-journal from the first list, obtain a lock on the globally ascending identifier, write a current value of the globally ascending identifier as a journal commit identifier into a header of the micro-journal, and write journal entries into the micro-journal corresponding to the plurality of modifications included in the transaction. The computer system can then commit the micro-journal to the byte-addressable persistent memory, increment the current value of the globally ascending identifier, and release the lock.

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