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公开(公告)号：US11586545B2
公开(公告)日：2023-02-21
申请号：US17367048
申请日：2021-07-02
申请人： VMware, Inc.
发明人： Irina Calciu , Andreas Nowatzyk , Isam Wadih Akkawi , Venkata Subhash Reddy Peddamallu , Pratap Subrahmanyam
IPC分类号： G06F12/0862
摘要： Memory pages of a local application program are prefetched from a memory of a remote host. A method of prefetching the memory pages from the remote memory includes detecting that a cache-line access made by a processor executing the local application program is an access to a cache line containing page table data of the local application program, identifying data pages that are referenced by the page table data, and fetching the identified data pages from the remote memory and storing the fetched data pages in a local memory.
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2.发明授权公开(公告)号：US10929235B2
公开(公告)日：2021-02-23
申请号：US15881514
申请日：2018-01-26
申请人： VMware, Inc.
发明人： Pratap Subrahmanyam , Rajesh Venkatasubramanian , Kiran Tati , Qasim Ali , Marcos Aguilera , Irina Calciu , Venkata Subhash Reddy Peddamallu , Xavier Deguillard , Yi Yao
摘要： Techniques for achieving application high availability via crash-consistent asynchronous replication of persistent data are provided. In one set of embodiments, an application running on a computer system can, during runtime of the application: write persistent data to a local nonvolatile data store of the computer system, write one or more log entries comprising the persistent data to a local log region of the computer system, and asynchronously copy the one or more log entries to one or more remote destinations. Then, upon detecting a failure that prevents the application from continuing execution, the computer system can copy the local log region or a remaining portion thereof to the one or more remote destinations, where the copying is performed while the computer system runs on battery power and where the application is restarted on another computer system using a persistent state derived from the copied log entries.
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公开(公告)号：US20180321962A1
公开(公告)日：2018-11-08
申请号：US15586109
申请日：2017-05-03
申请人： VMware, Inc.
发明人： Venkata Subhash Reddy Peddamallu , Kiran Tati , Rajesh Venkatasubramanian , Pratap Subrahmanyam
CPC分类号： G06F9/45558 , G06F3/0604 , G06F3/0647 , G06F3/0685 , G06F9/5016 , G06F2009/45579 , G06F2009/45583
摘要： Techniques for implementing OS/hypervisor-based persistent memory are provided. In one embodiment, an OS or hypervisor running on a computer system can allocate a portion of the volatile memory of the computer system as a persistent memory allocation. The OS/hypervisor can further receive a signal from the computer system's BIOS indicating an AC power loss or cycle event and, in response to the signal, can save data in the persistent memory allocation to a nonvolatile backing store. Then, upon restoration of AC power to the computer system, the OS/hypervisor can restore the saved data from the nonvolatile backing store to the persistent memory allocation.
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公开(公告)号：US11880309B2
公开(公告)日：2024-01-23
申请号：US17355941
申请日：2021-06-23
申请人： VMware, Inc.
发明人： Nishchay Dua , Andreas Nowatzyk , Isam Wadih Akkawi , Pratap Subrahmanyam , Venkata Subhash Reddy Peddamallu , Adarsh Seethanadi Nayak
IPC分类号： G06F12/0897 , G06F12/0831 , G06F12/0862
CPC分类号： G06F12/0897 , G06F12/0833 , G06F12/0862 , G06F2212/152
摘要： The state of cache lines transferred into an out of caches of processing hardware is tracked by monitoring hardware. The method of tracking includes monitoring the processing hardware for cache coherence events on a coherence interconnect between the processing hardware and monitoring hardware, determining that the state of a cache line has changed, and updating a hierarchical data structure to indicate the change in the state of said cache line. The hierarchical data structure includes a first level data structure including first bits, and a second level data structure including second bits, each of the first bits associated with a group of second bits. The step of updating includes setting one of the first bits and one of the second bits in the group corresponding to the first bit that is being set, according to an address of said cache line.
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公开(公告)号：US11782832B2
公开(公告)日：2023-10-10
申请号：US17411792
申请日：2021-08-25
申请人： VMware, Inc.
发明人： Isam Wadih Akkawi , Andreas Nowatzyk , Pratap Subrahmanyam , Nishchay Dua , Adarsh Seethanadi Nayak , Venkata Subhash Reddy Peddamallu , Irina Calciu
IPC分类号： G06F13/16 , G06F13/40 , G06F12/08 , G06F12/0804
CPC分类号： G06F12/0804 , G06F13/1668 , G06F13/4027 , G06F2212/1024 , G06F2212/1032
摘要： In a computer system, a processor and an I/O device controller communicate with each other via a coherence interconnect and according to a cache coherence protocol. Registers of the I/O device controllers are mapped to the cache coherent memory space to allow the processor to treat the registers as cacheable memory. As a result, latency of processor commands executed by the I/O device controller is decreased, and size of data stored in the I/O device controller that can be accessed by the processor is increased from the size of a single register to the size of an entire cache line.
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公开(公告)号：US11442865B1
公开(公告)日：2022-09-13
申请号：US17367078
申请日：2021-07-02
申请人： VMware, Inc.
发明人： Irina Calciu , Andreas Nowatzyk , Isam Wadih Akkawi , Venkata Subhash Reddy Peddamallu , Pratap Subrahmanyam
IPC分类号： G06F12/0862
摘要： A method of prefetching memory pages from remote memory includes detecting that a cache-line access made by a processor executing an application program is an access to a cache line containing page table data of the application program, identifying data pages that are referenced by the page table data, initiating a fetch of a data page, which is one of the identified data pages, and starting a timer. If the fetch completes prior to expiration of the timer, the data page is stored in a local memory. On the other hand, if the fetch does not complete prior to expiration of timer, a presence bit of the data page in the page table data is set to indicate that the data page is not present.
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7.发明申请公开(公告)号：US20190129812A1
公开(公告)日：2019-05-02
申请号：US15881379
申请日：2018-01-26
申请人： VMware, Inc.
发明人： Pratap Subrahmanyam , Rajesh Venkatasubramanian , Kiran Tati , Qasim Ali , Marcos Aguilera , Irina Calciu , Venkata Subhash Reddy Peddamallu , Xavier Deguillard , Yi Yao
摘要： Techniques for achieving application high availability via application-transparent battery-backed replication of persistent data are provided. In one set of embodiments, a computer system can detect a failure that causes an application of the computer system to stop running. In response to detecting the failure, the computer system can copy persistent data written by the application and maintained locally at the computer system to one or more remote destinations, where the copying is performed in a manner that is transparent to the application and while the computer system runs on battery power. The application can then be restarted on another computer system using the copied data.
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8.发明公开公开(公告)号：US20240028363A1
公开(公告)日：2024-01-25
申请号：US17871500
申请日：2022-07-22
申请人： VMware, Inc.
IPC分类号： G06F9/455
CPC分类号： G06F9/45558 , G06F2009/4557 , G06F2009/45562
摘要： The present disclosure relates to providing availability of passthrough devices configured on VCIs according to one or more embodiments of the present disclosure. One method includes receiving a notification of a failure associated with a passthrough device configured on a VCI, communicating, to the VCI, a simulation of a surprise hot removal of the device from the VCI, resetting the device, communicating, to the VCI, a simulation of a surprise hot add of the device to the VCI, and hot adding the device to the VCI.
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9.发明申请公开(公告)号：US20220027231A1
公开(公告)日：2022-01-27
申请号：US17494826
申请日：2021-10-05
申请人： VMware, Inc.
发明人： Sowgandh Sunil Gadi , Rajesh Venkatasubramanian , Venkata Subhash Reddy Peddamallu , Arunachalam Ramanathan , Timothy P Mann , Frederick Joseph Jacobs
摘要： Techniques for migrating virtual machines (VMs) in the presence of uncorrectable memory errors are provided. According to one set of embodiments, a source host hypervisor of a source host system can determine, for each guest memory page of a VM to be migrated from the source host system to a destination host system, whether the guest memory page is impacted by an uncorrectable memory error in a byte-addressable memory of the source host system. If the source host hypervisor determines that the guest memory page is impacted, the source host hypervisor can transmit a data packet to a destination host hypervisor of the destination host system that includes error metadata identifying the guest memory page as being corrupted. Alternatively, if the source host hypervisor determines that the guest memory page is not impacted, the source host hypervisor can attempt to read the guest memory page from the byte-addressable memory in a memory exception-safe manner.
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10.发明授权公开(公告)号：US11169870B2
公开(公告)日：2021-11-09
申请号：US16743895
申请日：2020-01-15
申请人： VMware, Inc.
发明人： Sowgandh Sunil Gadi , Rajesh Venkatasubramanian , Venkata Subhash Reddy Peddamallu , Arunachalam Ramanathan , Timothy P. Mann , Frederick Joseph Jacobs
摘要： Techniques for migrating virtual machines (VMs) in the presence of uncorrectable memory errors are provided. According to one set of embodiments, a source host hypervisor of a source host system can determine, for each guest memory page of a VM to be migrated from the source host system to a destination host system, whether the guest memory page is impacted by an uncorrectable memory error in a byte-addressable memory of the source host system. If the source host hypervisor determines that the guest memory page is impacted, the source host hypervisor can transmit a data packet to a destination host hypervisor of the destination host system that includes error metadata identifying the guest memory page as being corrupted. Alternatively, if the source host hypervisor determines that the guest memory page is not impacted, the source host hypervisor can attempt to read the guest memory page from the byte-addressable memory in a memory exception-safe manner.
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