Charge trap memory device with blocking insulating layer having higher-dielectric constant and larger energy band-gap and method of manufacturing the same
    52.
    发明申请
    Charge trap memory device with blocking insulating layer having higher-dielectric constant and larger energy band-gap and method of manufacturing the same 审中-公开
    具有较高介电常数和较大能带隙的阻挡绝缘层的电荷陷阱存储器及其制造方法

    公开(公告)号:US20080185633A1

    公开(公告)日:2008-08-07

    申请号:US12068060

    申请日:2008-02-01

    摘要: A charge trap memory device according to example embodiments may include a tunnel insulating layer provided on a substrate. A charge trap layer may be provided on the tunnel insulating layer. A blocking insulating layer may be provided on the charge trap layer, wherein the blocking insulating layer may include a lanthanide (e.g., lanthanum). The blocking insulating layer may further include aluminum and oxygen, wherein the ratio of lanthanide to aluminum may be greater than 1 (e.g., about 1.5 to about 2). The charge trap memory device may further include a buffer layer provided between the charge trap layer and the blocking insulating layer, and a gate electrode provided on the blocking insulating layer.

    摘要翻译: 根据示例性实施例的电荷陷阱存储器件可以包括设置在衬底上的隧道绝缘层。 电荷陷阱层可以设置在隧道绝缘层上。 阻挡绝缘层可以设置在电荷陷阱层上,其中阻挡绝缘层可以包括镧系元素(例如镧)。 阻挡绝缘层可以进一步包括铝和氧,其中镧系元素与铝的比可以大于1(例如约1.5至约2)。 电荷陷阱存储器件还可以包括设置在电荷陷阱层和阻挡绝缘层之间的缓冲层,以及设置在阻挡绝缘层上的栅电极。

    Semiconductor memory device including recessed control gate electrode
    53.
    发明申请
    Semiconductor memory device including recessed control gate electrode 失效
    半导体存储器件包括凹入控制栅电极

    公开(公告)号:US20080093662A1

    公开(公告)日:2008-04-24

    申请号:US11808982

    申请日:2007-06-14

    IPC分类号: H01L29/792

    摘要: A semiconductor memory device may include a semiconductor substrate, at least one control gate electrode, at least one storage node layer, at least one tunneling insulating layer, at least one blocking insulating layer, and/or first and second channel regions. The at least one control gate electrode may be recessed into the semiconductor substrate. The at least one storage node layer may be between a sidewall of the at least one control gate electrode and the semiconductor substrate. The at least one tunneling insulating layer may be between the at least one storage node layer and the at least one control gate electrode. The at least one blocking insulating layer may be between the storage node layer and the control gate electrode. The first and second channel regions may be between the at least one tunneling insulating layer and the semiconductor substrate to surround at least a portion of the sidewall of the control gate electrode and/or may be separated from each other.

    摘要翻译: 半导体存储器件可以包括半导体衬底,至少一个控制栅电极,至少一个存储节点层,至少一个隧道绝缘层,至少一个阻挡绝缘层和/或第一和第二沟道区。 至少一个控制栅电极可以凹进到半导体衬底中。 所述至少一个存储节点层可以在所述至少一个控制栅电极的侧壁和所述半导体衬底之间。 所述至少一个隧道绝缘层可以在所述至少一个存储节点层和所述至少一个控制栅电极之间。 所述至少一个阻挡绝缘层可以在所述存储节点层和所述控制栅电极之间。 第一和第二沟道区可以在至少一个隧道绝缘层和半导体衬底之间,以围绕控制栅电极的侧壁的至少一部分和/或可以彼此分离。