公开(公告)号：US20240321582A1

公开(公告)日：2024-09-26

申请号：US18680253

申请日：2024-05-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Guan-Xuan CHEN ,  Sheng-Liang PAN ,  Chia-Yang HUNG ,  Po-Chuan WANG ,  Huan-Just LIN

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/28247 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/02063 ,  H01L21/02175 ,  H01L21/02194 ,  H01L21/02332 ,  H01L21/0234

Abstract: A method for making a semiconductor device includes patterning at least one dielectric layer disposed over a conductive cap layer to form a via opening penetrating through the at least one dielectric layer to expose the conductive cap layer and to form a top portion of the conductive cap layer into a metal oxide layer; converting the metal oxide layer to a metal oxynitride layer by a soft ashing process using a processing gas containing nitrogen gas; removing the metal oxynitride layer from a remaining portion of the conductive cap layer; and forming a via contact in the via opening to electrically connect the remaining portion of the conductive cap layer.

公开(公告)号：US20240266469A1

公开(公告)日：2024-08-08

申请号：US18629555

申请日：2024-04-08

Applicant: Silanna UV Technologies Pte Ltd

Inventor： Petar Atanackovic

IPC: H01L33/26 ,  H01L21/02 ,  H01L23/66 ,  H01L27/15 ,  H01L29/15 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/51 ,  H01L29/66 ,  H01L29/778 ,  H01L29/786 ,  H01L33/00 ,  H01L33/06 ,  H01L33/16 ,  H01L33/18 ,  H01L33/62 ,  H01S5/34

CPC classification number: H01L33/26 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/02507 ,  H01L23/66 ,  H01L27/15 ,  H01L29/151 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7869 ,  H01L33/002 ,  H01L33/007 ,  H01L33/06 ,  H01L33/16 ,  H01L33/18 ,  H01L33/62 ,  H01S5/34 ,  H01L29/778 ,  H01L29/7786 ,  H01L2223/6627

Abstract: The techniques described herein relate to a transistor including a substrate including sapphire, an epitaxial channel layer on the substrate, and an epitaxial gate layer on the channel layer. The epitaxial channel layer can include α-Ga2O3, with a first bandgap. The epitaxial gate layer can include an oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap. The transistor can also include electrical contacts, including: a source electrical contact coupled to the epitaxial channel layer; a drain electrical contact coupled to the epitaxial channel layer; and a gate electrical contact coupled to the epitaxial gate layer.

公开(公告)号：US20240258460A1

公开(公告)日：2024-08-01

申请号：US18629606

申请日：2024-04-08

Applicant: Silanna UV Technologies Pte Ltd

Inventor： Petar Atanackovic

IPC: H01L33/26 ,  H01L21/02 ,  H01L23/66 ,  H01L27/15 ,  H01L29/15 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/51 ,  H01L29/66 ,  H01L29/778 ,  H01L29/786 ,  H01L33/00 ,  H01L33/06 ,  H01L33/16 ,  H01L33/18 ,  H01L33/62 ,  H01S5/34

CPC classification number: H01L33/26 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/02507 ,  H01L23/66 ,  H01L27/15 ,  H01L29/151 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7869 ,  H01L33/002 ,  H01L33/007 ,  H01L33/06 ,  H01L33/16 ,  H01L33/18 ,  H01L33/62 ,  H01S5/34 ,  H01L29/778 ,  H01L29/7786 ,  H01L2223/6627

Abstract: The techniques described herein relate to a transistor, including a substrate, an epitaxial buffer layer, an epitaxial channel layer, and a gate layer. The substrate includes a first oxide material with a first crystal symmetry, the epitaxial buffer layer includes a second oxide material with a second crystal symmetry, the epitaxial channel layer includes a third oxide material with a third crystal symmetry and a first bandgap, and the gate layer includes a fourth oxide material with a second bandgap. The first crystal symmetry is different from either the second crystal symmetry or the third crystal symmetry, and the second bandgap is wider than the first bandgap. The transistor also includes electrical contacts including a source electrical contact coupled to the epitaxial channel layer, a drain electrical contact coupled to the epitaxial channel layer, and a gate electrical contact coupled to the gate layer.

公开(公告)号：US12033860B2

公开(公告)日：2024-07-09

申请号：US17377864

申请日：2021-07-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Guan-Xuan Chen ,  Sheng-Liang Pan ,  Chia-Yang Hung ,  Po-Chuan Wang ,  Huan-Just Lin

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/28247 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/02063 ,  H01L21/02175 ,  H01L21/02194 ,  H01L21/02332 ,  H01L21/0234

Abstract: A method for making a semiconductor device includes patterning at least one dielectric layer disposed over a conductive cap layer to form a via opening penetrating through the at least one dielectric layer to expose the conductive cap layer and to form a top portion of the conductive cap layer into a metal oxide layer; converting the metal oxide layer to a metal oxynitride layer by a soft ashing process using a processing gas containing nitrogen gas; removing the metal oxynitride layer from a remaining portion of the conductive cap layer; and forming a via contact in the via opening to electrically connect the remaining portion of the conductive cap layer.

公开(公告)号：US11972941B2

公开(公告)日：2024-04-30

申请号：US17288604

申请日：2019-12-06

Applicant: SK TRICHEM

Inventor： Chang Sung Hong ,  Yong Joo Park ,  Tae Hoon Oh ,  In Chun Hwang ,  Sang Kyung Lee ,  Dong Hyun Kim

IPC: H01L29/02 ,  C07F7/00 ,  C07F17/00 ,  C23C16/18 ,  C23C16/455 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L21/02205 ,  C07F7/00 ,  C23C16/18 ,  C23C16/45553 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/28194 ,  H01L29/517 ,  C23C16/45536

Abstract: Proposed is a precursor composition for forming a metal film including a zirconium compound represented by any one of Chemical Formulas 1 to 3 and a hafnium compound represented by any one of Chemical Formulas 4 to 6.

公开(公告)号：US11961897B2

公开(公告)日：2024-04-16

申请号：US17572267

申请日：2022-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Hsing Hsu ,  Sai-Hooi Yeong ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Min Cao

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L29/516 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/517

Abstract: A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.

公开(公告)号：US20230420247A1

公开(公告)日：2023-12-28

申请号：US18037407

申请日：2022-01-06

Applicant: THE UNIVERSITY OF HONG KONG

Inventor： Dong HUANG ,  Chi Chung Francis LING

IPC: H01L21/02

CPC classification number: H01L21/02266 ,  H01L21/02189 ,  H01L21/02194

Abstract: A thin film (Ga 0.5%, Cu 8%) co-doped ZnO with high dielectric constant and high optical transmittance in the visible light range is formed via a pulse laser deposition method. The steps of the method involve installing a sapphire based substrate mounted on a sample holder into a pulse laser deposition chamber; and installing a ZnO ceramic target containing designed Ga and Cu concentrations in the chamber. Then the chamber is evacuated until the pressure achieves 5e-4 Pa., at which point the substrate is heated to about 600 degrees C. Next oxygen gas is introduced into the chamber and adjusted to a pressure of about 5 Pa. The rotation speed of the substrate holder and target holder are adjusted to about 10 r/min. Finally, the laser beam is applied to the target to ablate it sufficiently to generate a plasma of ionized atoms that are deposited on the substrate to form the film with the same composition same as the target.

公开(公告)号：US11784235B2

公开(公告)日：2023-10-10

申请号：US17826529

申请日：2022-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Hsing Hsu ,  Sai-Hooi Yeong ,  Chih-Yu Chang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/51 ,  H01L21/28 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/516 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78 ,  H01L29/78391 ,  H01L29/4232 ,  H01L29/66545

Abstract: A negative capacitance semiconductor device includes a substrate. A dielectric layer is disposed over a portion of the substrate. A ferroelectric structure is disposed over the dielectric layer. Within the ferroelectric structure: a material composition of the ferroelectric structure varies as a function of a height within the ferroelectric structure. A gate electrode is disposed over the ferroelectric structure.

公开(公告)号：US11769664B2

公开(公告)日：2023-09-26

申请号：US17577073

申请日：2022-01-17

Applicant: ASM IP Holding B.V.

Inventor： Tatiana Ivanova ,  Perttu Sippola ,  Michael Eugene Givens

IPC: H01L21/02 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L21/02194 ,  H01L21/0228 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/02205 ,  H01L21/02356 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/517

Abstract: A method for depositing a hafnium lanthanum oxide film on a substrate by a cyclical deposition in a reaction chamber is disclosed. The method may include: depositing a hafnium oxide film on the substrate utilizing a first sub-cycle of the cyclical deposition process and depositing a lanthanum oxide film utilizing a second sub-cycle of the cyclical deposition process.

公开(公告)号：US20230282521A1

公开(公告)日：2023-09-07

申请号：US18318195

申请日：2023-05-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kun-Yu LEE ,  Chunyao WANG ,  Chi On CHUI

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/823481 ,  H01L27/0886 ,  H01L21/02356 ,  H01L21/76224 ,  H01L21/02271 ,  H01L21/022 ,  H01L21/02148 ,  H01L21/02181 ,  H01L21/02194 ,  H01L21/02183 ,  H01L21/02192 ,  H01L21/02189 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/0214

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure over a semiconductor substrate and a first epitaxial structure over the first fin structure. The semiconductor device structure also includes a second epitaxial structure over the second fin structure. The semiconductor device structure further includes a dielectric fin over the semiconductor substrate. The dielectric fin is between the first fin structure and the second fin structure. The dielectric fin has an inner portion and a protective layer. The protective layer extends along sidewalls and a bottom of the inner portion, and the protective layer has a dielectric constant higher than that of the inner portion.