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    METHOD AND APPARATUS FOR STATISTICAL CMOS DEVICE CHARACTERIZATION
    51.
    发明申请
    METHOD AND APPARATUS FOR STATISTICAL CMOS DEVICE CHARACTERIZATION 失效
    用于统计CMOS器件特征的方法和装置

    公开(公告)号：US20100225348A1

    公开(公告)日：2010-09-09

    申请号：US12779038

    申请日：2010-05-12

    申请人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

    发明人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

    IPC分类号： G01R31/26

    CPC分类号： G01R31/3181 ,  G01R31/3004

    摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

    摘要翻译： 使用具有大量被测电子器件的统一测试结构来表征器件的电容电压参数（C-V）和电流 - 电压参数（I-V）。 这些器件被排列成列和行的阵列，并由控制逻辑选择，该逻辑门将不同地作为电流源，吸收器，钳位，测量端口和检测线的输入/输出引脚进行门控。 通过对不同的激发电压频率进行基线和激励电流测量来测量电容电压参数，计算基线和激励电流测量之间的电流差异，并产生电流差与不同频率之间的线性关系。 然后通过将表示线性关系的线的斜率除以激励电压来导出电容。 可以对不同的电子设备进行测试，包括晶体管和互连结构。

    Method and apparatus for statistical CMOS device characterization
    52.
    发明授权
    Method and apparatus for statistical CMOS device characterization 失效

    公开(公告)号：US07782076B2

    公开(公告)日：2010-08-24

    申请号：US12141862

    申请日：2008-06-18

    申请人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

    发明人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

    IPC分类号： G01R31/26 ,  G01R31/28

    CPC分类号： G01R31/3181 ,  G01R31/3004

    摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

    Illumination module, and a display and general lighting apparatus using the same
    53.
    发明申请
    Illumination module, and a display and general lighting apparatus using the same 有权
    照明模块，以及使用其的显示器和通用照明装置

    公开(公告)号：US20090273946A1

    公开(公告)日：2009-11-05

    申请号：US12290340

    申请日：2008-10-28

    申请人： Ying Liu ,  Pak-Hong Ng ,  Shou-Lung Chen

    发明人： Ying Liu ,  Pak-Hong Ng ,  Shou-Lung Chen

    IPC分类号： F21V7/22

    CPC分类号： G02F1/133604 ,  G02F1/133605 ,  G02F1/133611

    摘要： The present invention provides an illumination module, and a display and a general lighting apparatus using the same. Said illumination module includes a plurality of light guiding strips arranged in juxtaposition with a predefined distance; a plurality of light sources, disposed on at least one end of said light guiding strips respectively for providing the light into said light guiding strips; and a plurality of light reflecting units, disposed between said light guiding strips for reflecting the light from said light guiding strips. The light reflecting units according to the present invention can guide the light from the sides of light guiding strips or other light not toward the right side of the illumination module back to the right side of the illumination module, and thus improving the light output efficiency and uniformity.

    摘要翻译： 本发明提供了一种照明模块，以及使用其的显示器和一般照明装置。 所述照明模块包括以预定距离并列布置的多个导光条; 多个光源，分别设置在所述导光条的至少一端，用于将光提供到所述导光条中; 以及多个光反射单元，设置在所述导光条之间，用于反射来自所述导光条的光。 根据本发明的光反射单元可以将来自导光条或其他光的侧面的光引导到照明模块的右侧，直到照明模块的右侧，从而提高光输出效率， 均匀性

    Apparatus and method for handwriting recognition
    55.
    发明授权
    Apparatus and method for handwriting recognition 有权
    手写识别的装置和方法

    公开(公告)号：US07580029B2

    公开(公告)日：2009-08-25

    申请号：US10817287

    申请日：2004-04-02

    申请人： Ying Liu ,  Jari A. Kangas ,  Zou Yanming ,  Gao Yipu

    发明人： Ying Liu ,  Jari A. Kangas ,  Zou Yanming ,  Gao Yipu

    IPC分类号： G09G5/00

    CPC分类号： G06F3/04883 ,  G06F3/0488 ,  G06F3/04886

    摘要： An apparatus for handwriting recognition has a touch-sensitive display screen providing a handwriting input area capable of detecting a handwritten user input. The apparatus also has a processing device configured to interpret the handwritten user input as a symbol from a plurality of predefined symbols. The handwriting input area includes a writing start area, and the processing device is configured to provide a visual indication of the writing start area on the display screen. The processing device is configured to interpret the user input as a symbol only if the user input starts within the writing start area.

    摘要翻译： 一种用于手写识别的装置具有提供能够检测手写用户输入的手写输入区域的触敏显示屏。 该装置还具有配置成将手写用户输入从多个预定符号中解读为符号的处理装置。 手写输入区域包括写入开始区域，并且处理装置被配置为在显示屏幕上提供写入开始区域的视觉指示。 处理装置被配置为仅当用户输入在写入开始区域内开始时将用户输入解释为符号。

    CHARGE-BASED CIRCUIT ANALYSIS
    56.
    发明申请
    CHARGE-BASED CIRCUIT ANALYSIS 有权
    基于费率的电路分析

    公开(公告)号：US20090192776A1

    公开(公告)日：2009-07-30

    申请号：US12163318

    申请日：2008-06-27

    申请人： Emrah Acar ,  Bhavna Agrawal ,  Peter Feldmann ,  Ying Liu ,  Steven G. Walker

    发明人： Emrah Acar ,  Bhavna Agrawal ,  Peter Feldmann ,  Ying Liu ,  Steven G. Walker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A solution for analyzing a circuit using initial charge information is provided. In particular, one or more nodes in a design for the circuit is initialized with an initial charge. The charge can comprise a non-equilibrium charge, thereby simulating the history effect, the impact of a charged particle, electro-static discharge (ESD), and/or the like. Operation of the circuit is then simulated over a set of input cycles based on the initial charge(s). To this extent, the non-equilibrium initial condition solution enables the state of the circuit to be controlled and solves the initial system based on these values. This capability is very useful to condition the circuit at a worst-case, best-case, and/or the like, status. Further, in one embodiment of the invention, a set of equations are provided to implement the non-equilibrium initial charge analysis, which provide a more efficient initialization of the circuit than current solutions.

    摘要翻译： 提供了使用初始电荷信息分析电路的解决方案。 特别地，用于电路的设计中的一个或多个节点用初始电荷初始化。 电荷可以包括非平衡电荷，从而模拟历史效应，带电粒子的影响，静电放电（ESD）等。 然后基于初始电荷在一组输入周期上模拟电路的操作。 在这种程度上，非平衡初始条件解决方案使得能够控制电路的状态并且基于这些值来解决初始系统。 该功能对于在最坏情况，最佳情况和/或类似状态下调节电路非常有用。 此外，在本发明的一个实施例中，提供一组方程以实现非平衡初始电荷分析，其提供电路比当前解决方案更有效的初始化。

    Charge-based circuit analysis
    59.
    发明授权
    Charge-based circuit analysis 失效
    充电电路分析

    公开(公告)号：US07519526B2

    公开(公告)日：2009-04-14

    申请号：US11355342

    申请日：2006-02-16

    申请人： Emrah Acar ,  Bhavna Agrawal ,  Peter Feldmann ,  Ying Liu ,  Steven G. Walker

    发明人： Emrah Acar ,  Bhavna Agrawal ,  Peter Feldmann ,  Ying Liu ,  Steven G. Walker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A solution for analyzing a circuit using initial charge information is provided. In particular, one or more nodes in a design for the circuit is initialized with an initial charge. The charge can comprise a non-equilibrium charge, thereby simulating the history effect, the impact of a charged particle, electro-static discharge (ESD), and/or the like. Operation of the circuit is then simulated over the set of input cycles based on the initial charge(s). To this extent, the non-equilibrium initial condition solution enables the state of the circuit to be controlled and solves the initial system based on these values. This capability is very useful to condition the circuit at a worst-case, best-case, and/or the like, status. Further, in one embodiment of the invention, a set of equations are provided to implement the non-equilibrium initial charge analysis, which provide a more efficient initialization of the circuit than current solutions.

    摘要翻译： 提供了使用初始电荷信息分析电路的解决方案。 特别地，用于电路的设计中的一个或多个节点用初始电荷初始化。 电荷可以包括非平衡电荷，从而模拟历史效应，带电粒子的影响，静电放电（ESD）等。 然后基于初始充电在该组输入周期上模拟电路的操作。 在这种程度上，非平衡初始条件解决方案使得能够控制电路的状态并且基于这些值来解决初始系统。 该功能对于在最坏情况，最佳情况和/或类似状态下调节电路非常有用。 此外，在本发明的一个实施例中，提供一组方程以实现非平衡初始电荷分析，其提供电路比当前解决方案更有效的初始化。

    Closed-Loop Modeling of Gate Leakage for Fast Simulators
    60.
    发明申请
    Closed-Loop Modeling of Gate Leakage for Fast Simulators 有权
    闸模泄漏闭环建模快速模拟器

    公开(公告)号：US20080281570A1

    公开(公告)日：2008-11-13

    申请号：US11746976

    申请日：2007-05-10

    申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Ying Liu ,  Sani R. Nassif ,  Jayakumaran Sivagnaname

    发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Ying Liu ,  Sani R. Nassif ,  Jayakumaran Sivagnaname

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A method for circuit simulation using a netlist in which a first device having an unmodeled, nonlinear behavior is modified by inserting a second device which has a nonlinear response approximating the unmodeled nonlinear behavior. The first device may be for example a first transistor and the second device may be a variable current source, in particular one whose current is modeled after a floating transistor template which represents gate leakage current of the first transistor (gate-to-source or gate-to-drain). During simulation of the circuit a parameter such as a gate-to-source voltage of the second transistor is controlled to model gate leakage. The model parameters can be a function of an effective quantum mechanical oxide thickness value of a gate of the first transistor technology.

    摘要翻译： 一种使用网表的电路仿真方法，其中具有未建模的非线性行为的第一器件通过插入具有接近未建模的非线性行为的非线性响应的第二器件而被修改。 第一器件可以是例如第一晶体管，并且第二器件可以是可变电流源，特别是其中电流在表示第一晶体管（栅极至源极或栅极 -排水）。 在仿真电路期间，控制诸如第二晶体管的栅极至源极电压的参数来模拟栅极泄漏。 模型参数可以是第一晶体管技术的栅极的有效量子机械氧化物厚度值的函数。