公开(公告)号：US20140095735A1

公开(公告)日：2014-04-03

申请号：US13902967

申请日：2013-05-27

申请人： PixArt Imaging Inc.

发明人： Chih-Yen Wu

IPC分类号： G06F3/06

CPC分类号： G06F3/0659 ,  G06F3/061 ,  G06F3/0673 ,  G06F13/385 ,  G06F2213/3854

摘要： A communication method applied to a transmission port between an access device and a control device includes: encoding a specific command to generate mode data; generating output data according to content of the mode data and content of command data corresponding to the specific command; and transmitting the output data from one of the access device and control device to the other via the transmission port. The other device of the access device and control device is used for receiving the output data and decoding the mode data of the output data to generate a decoding result, and selecting the specific command from a plurality of operational commands for executing a communication function corresponding to the specific command according to the decoding result.

摘要翻译： 应用于接入设备和控制设备之间的传输端口的通信方法包括：对特定命令进行编码以生成模式数据; 根据模式数据的内容和对应于特定命令的命令数据的内容生成输出数据; 并且经由所述传输端口将所述输入数据从所述接入设备和控制设备之一发送到另一个。 访问设备和控制设备的另一设备用于接收输出数据并解码输出数据的模式数据以产生解码结果，并从多个操作命令中选择特定命令，以执行对应于 具体命令根据解码结果。

公开(公告)号：US20110185207A1

公开(公告)日：2011-07-28

申请号：US12692756

申请日：2010-01-25

申请人： Thanga Anandappan ,  Balamurugan Manickam ,  Hemanth R.S

发明人： Thanga Anandappan ,  Balamurugan Manickam ,  Hemanth R.S

IPC分类号： G06F13/20 ,  G06F13/366 ,  G06F1/32 ,  G06F1/26

CPC分类号： G06F1/3209 ,  G06F1/3228 ,  G06F2213/3804 ,  G06F2213/3854

摘要： A method to facilitate data transfer to a line replaceable unit that lacks a transmission control protocol/Internet protocol (TCP/IP) interface is provided. The method comprises interfacing a memory-processing card to the line replaceable unit. The memory-processing card includes a memory, a central processing unit module, an interface to the line replaceable unit, an interface to an access point communicatively coupled to the central processing unit module, and a bus arbitrator communicatively coupled to the memory, the central processing unit module, and the interfaces. The method also includes determining a state of the line replaceable unit at the bus arbitrator responsive to the interfacing, providing access at the bus arbitrator from the central processing unit module to the memory when the determined state of the line replaceable unit is OFF, and providing access at the bus arbitrator from the line replaceable unit to the memory when the determined state of the line replaceable unit is ON.

摘要翻译： 提供了一种方便数据传输到缺少传输控制协议/互联网协议（TCP / IP）接口的线路可更换单元的方法。 该方法包括将存储处理卡连接到线路可更换单元。 存储处理卡包括存储器，中央处理单元模块，到线路可替换单元的接口，到通信地耦合到中央处理单元模块的接入点的接口以及通信地耦合到存储器的总线仲裁器，中心 处理单元模块和接口。 该方法还包括响应于接口在总线仲裁器处确定线路可替换单元的状态，当线路可替换单元的确定状态为OFF时，在总线仲裁器处从中央处理单元模块向存储器提供访问，并且提供 当线路可更换单元的确定状态为ON时，将总线仲裁器从线路可更换单元接入存储器。

公开(公告)号：US20110087836A1

公开(公告)日：2011-04-14

申请号：US12897990

申请日：2010-10-05

申请人： Kenichi Nakanishi ,  Keiichi Tsutsui ,  Junichi Koshiyama

发明人： Kenichi Nakanishi ,  Keiichi Tsutsui ,  Junichi Koshiyama

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F13/385 ,  G06F12/0893 ,  G06F2213/3854

摘要： A storage unit includes: a random access memory device and a storage device to be accessed using an address in units of word and sector, respectively; and a storage controller controlling accesses to the random access memory device and the storage device according to the addresses designated via a bus. The storage controller includes first and second interface functions for access to data stored on the storage device and the random access memory designated using the sector address and the word address provided via the bus, respectively, a function of using the random access memory device as a first disk cache and determining data to be saved in the random access memory device in response to the access by the first interface function, and functions of transferring the data designated using the sector address by repeating register access and by a bus master function as continuous word-sized data through the bus.

摘要翻译： 存储单元包括：随机存取存储器装置和存储装置，分别以字和扇区为单位使用地址进行访问; 以及存储控制器，其根据经由总线指定的地址来控制对所述随机存取存储器件和所述存储装置的访问。 存储控制器包括用于访问存储在存储设备上的数据的第一和第二接口功能以及使用经由总线提供的扇区地址和字地址指定的随机存取存储器，使用随机存取存储器件作为 第一磁盘高速缓存并且响应于第一接口功能的访问而确定要存储在随机存取存储器装置中的数据，以及通过重复寄存器访问和通过总线主机功能作为连续字传送使用扇区地址指定的数据的功能 通过总线的尺寸数据。

公开(公告)号：US20110022783A1

公开(公告)日：2011-01-27

申请号：US12509405

申请日：2009-07-24

申请人： Mark MOSHAYEDI

发明人： Mark MOSHAYEDI

IPC分类号： G06F12/00 ,  G06F13/14 ,  G06F12/02

CPC分类号： G06F13/385 ,  G06F2212/7208 ,  G06F2213/3854

摘要： A flash storage system includes a flash storage controller coupled to storage modules of a flash storage array via universal serial buses. Each storage module includes at least one flash memory device. The flash storage controller receives a programming command of a communication protocol and generates universal serial bus commands based on the programming command. The flash storage controller issues the universal serial bus commands to storage modules in the flash storage array via the universal serial buses. The storage modules process the universal serial bus commands to access data in the flash storage devices of the storage modules.

摘要翻译： 闪存存储系统包括通过通用串行总线耦合到闪存阵列的存储模块的闪存控制器。 每个存储模块包括至少一个闪存器件。 闪存控制器接收通信协议的编程命令，并根据编程命令生成通用串行总线命令。 闪存控制器通过通用串行总线向闪存阵列中的存储模块发出通用串行总线命令。 存储模块处理通用串行总线命令以访问存储模块的闪存存储设备中的数据。