摘要:
A sensor circuit is provided with a chopper-stabilized amplifier circuit configured to receive a signal from at least one magnetic sensing element, a sigma-delta modulator (SDM) configured to receive a signal from the chopper-stabilized amplifier circuit, and a feedback circuit configured to reduce ripple in a signal generated by the chopper-stabilized amplifier circuit. The feedback circuit includes a demodulator to demodulate a signal from the SDM in a digital domain by inverting a bit stream of the signal from the SDM according to a frequency chopping rate, a digital integrator configured to integrate an output signal of the demodulator to form an integrated signal, and a digital-to-analog converter (DAC) configured to convert the integrated signal to an analog signal and provide the analog signal to the chopper-stabilized amplifier circuit.
摘要:
Circuitry, which includes data memory and processing circuitry, is disclosed. The data memory is used to store look-up table (LUT)-based radio frequency (RF) power amplifier (PA) calibration data. The processing circuitry converts at least a portion of the LUT-based RF PA calibration data to provide monotonic response curve-based data. As such, a magnitude of an envelope power supply control signal is determined based on a magnitude of an RF input signal using the monotonic response curve-based data.
摘要:
An amplifier may include two or more pulse-width modulators (PWMs) controlling respective sets of switches to produce an amplified version of a source signal. The clocking for the amplifier may be controlled to delay signal processing within the PWMs relative to one another in time, thereby providing an effective time offset between the absolute moment in time of the edge transition of the controlling signals to the respective sets of switches. The PWMs may include a decrementor that counts down to zero from the next PWM duty-cycle value when a new data sample is detected, beginning a new count when the next sample is present. The PWM output may correspond to the counter value, outputting a pulse when the counter value is nonzero. A “data-sample-ready” signal may be decoded from a master counter, which may be clocked based on the high speed PWM clock, and the delay mechanism may be based on adjusting the decode value to determine when the PWM should initialize to the next data sample.
摘要:
Power detectors with temperature compensation and having improved accuracy over temperature are disclosed. In an aspect of the disclosure, variations of a power detector gain over temperature is reduced by varying both the gate and drain voltages of MOS transistors within a power detector. In an exemplary design, an apparatus includes at least one MOS transistor, which receives an input signal, detects the power of the input signal based on a power detection gain, and provides an output signal indicative of the power of the input signal. The at least one MOS transistor is applied a variable gate bias voltage and a variable drain bias voltage in order to reduce variations of the power detection gain over temperature. At least one additional MOS transistor may receive a second variable gate bias voltage and provide the variable drain bias voltage for the at least one MOS transistor.