55.
    发明授权
    失效

    公开(公告)号:US1963161A

    公开(公告)日:1934-06-19

    申请号:US1963161D

    IPC分类号: H03G1/04

    CPC分类号: H03G1/04

    Monotonic conversion of RF power amplifier calibration data
    58.
    发明授权
    Monotonic conversion of RF power amplifier calibration data 有权
    射频功率放大器校准数据的单调转换

    公开(公告)号:US08975959B2

    公开(公告)日:2015-03-10

    申请号:US13684826

    申请日:2012-11-26

    发明人: Nadim Khlat

    摘要: Circuitry, which includes data memory and processing circuitry, is disclosed. The data memory is used to store look-up table (LUT)-based radio frequency (RF) power amplifier (PA) calibration data. The processing circuitry converts at least a portion of the LUT-based RF PA calibration data to provide monotonic response curve-based data. As such, a magnitude of an envelope power supply control signal is determined based on a magnitude of an RF input signal using the monotonic response curve-based data.

    摘要翻译: 公开了包括数据存储器和处理电路的电路。 数据存储器用于存储基于查找表(LUT)的射频(RF)功率放大器(PA)校准数据。 处理电路将基于LUT的RF PA校准数据的至少一部分转换为提供基于单调响应曲线的数据。 因此,使用基于单调响应曲线的数据,基于RF输入信号的大小来确定包络电源控制信号的幅度。

    Noise and Cross-Talk Attenuation in an Audio System by Offsetting Outputs in Phase
    59.
    发明申请
    Noise and Cross-Talk Attenuation in an Audio System by Offsetting Outputs in Phase 审中-公开
    音频系统中的噪声和串扰衰减通过在相位上偏移输出

    公开(公告)号:US20150063593A1

    公开(公告)日:2015-03-05

    申请号:US14490459

    申请日:2014-09-18

    IPC分类号: H03G3/30 H03G1/04

    摘要: An amplifier may include two or more pulse-width modulators (PWMs) controlling respective sets of switches to produce an amplified version of a source signal. The clocking for the amplifier may be controlled to delay signal processing within the PWMs relative to one another in time, thereby providing an effective time offset between the absolute moment in time of the edge transition of the controlling signals to the respective sets of switches. The PWMs may include a decrementor that counts down to zero from the next PWM duty-cycle value when a new data sample is detected, beginning a new count when the next sample is present. The PWM output may correspond to the counter value, outputting a pulse when the counter value is nonzero. A “data-sample-ready” signal may be decoded from a master counter, which may be clocked based on the high speed PWM clock, and the delay mechanism may be based on adjusting the decode value to determine when the PWM should initialize to the next data sample.

    摘要翻译: 放大器可以包括两个或更多个脉冲宽度调制器(PWM),其控制各组开关以产生源信号的放大版本。 可以控制放大器的时钟,以在时间上相对于彼此延迟PWM内的信号处理,从而在控制信号的边沿转换到相应的开关组之间的绝对时刻之间提供有效的时间偏移。 当检测到新的数据样本时,PWM可以包括从下一个PWM占空比值向下递减到零的递减器,当存在下一个采样时,开始新的计数。 PWM输出可对应于计数器值,当计数器值不为零时输出脉冲。 可以从主计数器解码“数据采样就绪”信号,该主计数器可以基于高速PWM时钟来计时,并且延迟机制可以基于调整解码值来确定PWM何时应该初始化为 下一个数据样本。

    Power detector with temperature compensation
    60.
    发明授权
    Power detector with temperature compensation 有权
    带温度补偿功率检测器

    公开(公告)号:US08897727B2

    公开(公告)日:2014-11-25

    申请号:US13828714

    申请日:2013-03-14

    摘要: Power detectors with temperature compensation and having improved accuracy over temperature are disclosed. In an aspect of the disclosure, variations of a power detector gain over temperature is reduced by varying both the gate and drain voltages of MOS transistors within a power detector. In an exemplary design, an apparatus includes at least one MOS transistor, which receives an input signal, detects the power of the input signal based on a power detection gain, and provides an output signal indicative of the power of the input signal. The at least one MOS transistor is applied a variable gate bias voltage and a variable drain bias voltage in order to reduce variations of the power detection gain over temperature. At least one additional MOS transistor may receive a second variable gate bias voltage and provide the variable drain bias voltage for the at least one MOS transistor.

    摘要翻译: 公开了具有温度补偿并且具有提高的温度精度的功率检测器。 在本公开的一个方面,通过改变功率检测器内的MOS晶体管的栅极和漏极电压来降低功率检测器的增益随温度的变化。 在示例性设计中,一种装置包括至少一个MOS晶体管,其接收输入信号,基于功率检测增益来检测输入信号的功率,并提供表示输入信号功率的输出信号。 至少一个MOS晶体管被施加可变栅极偏置电压和可变漏极偏置电压,以便减小功率检测增益随温度的变化。 至少一个附加MOS晶体管可以接收第二可变栅极偏置电压,并为至少一个MOS晶体管提供可变漏极偏置电压。