公开(公告)号：US08369150B2

公开(公告)日：2013-02-05

申请号：US13018026

申请日：2011-01-31

Applicant: Lyle D. Jones ,  Roger W. Lindsay ,  Kirk D. Prall

Inventor： Lyle D. Jones ,  Roger W. Lindsay ,  Kirk D. Prall

IPC: G11C16/04

CPC classification number: H01L27/115 ,  G11C5/02 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11524

Abstract: A relaxed metal pitch architecture may include a bit line and a first active area string and a second active area string. The bit line may be directly coupled to the first active area string and to the second active area string. The relaxed metal pitch architecture may be applied to a non-volatile memory structure.

Abstract translation: 轻松的金属间距结构可以包括位线和第一有效区域串和第二有效区域串。 位线可以直接耦合到第一有效区域串和第二有效区域串。 轻松的金属间距结构可以应用于非易失性存储器结构。

公开(公告)号：US08330139B2

公开(公告)日：2012-12-11

申请号：US13072504

申请日：2011-03-25

Applicant: Durai Vishak Nirmal Ramaswamy ,  Kirk D. Prall

Inventor： Durai Vishak Nirmal Ramaswamy ,  Kirk D. Prall

IPC: H01L47/00 ,  H01L21/336 ,  G11C11/00

CPC classification number: H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147

Abstract: Some embodiments include a memory device and methods of forming the same. The memory device can include an electrode coupled to a memory element. The electrode can include different materials located at different portions of the electrode. The materials can create different dielectrics contacting the memory elements at different locations. Various states of the materials in the memory device can be used to represent stored information. Other embodiments are described.

Abstract translation: 一些实施例包括存储器件及其形成方法。 存储器件可以包括耦合到存储元件的电极。 电极可以包括位于电极的不同部分的不同材料。 这些材料可以在不同位置产生接触存储元件的不同电介质。 可以使用存储器件中的材料的各种状态来表示存储的信息。 描述其他实施例。

公开(公告)号：US20120007037A1

公开(公告)日：2012-01-12

申请号：US12833314

申请日：2010-07-09

Applicant: Nirmal Ramaswamy ,  Kirk D. Prall

Inventor： Nirmal Ramaswamy ,  Kirk D. Prall

IPC: H01L45/00

CPC classification number: H01L45/14 ,  G11C13/0004 ,  H01L27/24 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/145

Abstract: Memory devices utilizing memory cells including a resistive element and a diode coupled in series between two conductors. The diodes include a ruthenium material and a silicon material. The diodes further include an interface on the silicon material of ruthenium or ruthenium silicide. A ruthenium silicide interface may be a polycrystalline ruthenium silicide.

Abstract translation: 利用存储单元的存储器件，其中包括电阻元件和耦合在两个导体之间的二极管。 二极管包括钌材料和硅材料。 二极管还包括硅材料上的钌或钌化硅的界面。 硅化钌界面可以是多晶硅化钌。

公开(公告)号：US07897470B2

公开(公告)日：2011-03-01

申请号：US12496437

申请日：2009-07-01

Applicant: Gurtej S. Sandhu ,  Kirk D. Prall

Inventor： Gurtej S. Sandhu ,  Kirk D. Prall

IPC: H01L21/336

CPC classification number: H01L29/7881 ,  B82Y10/00 ,  G11C16/0408 ,  G11C2216/06 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/513

Abstract: A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming a second dielectric layer over the nanodots, where the second dielectric layer encases the nanodots. In addition, an intergate dielectric layer is formed over the second dielectric layer. To form sidewalls of the memory cell, a portion of the intergate dielectric layer and a portion of the second dielectric layer are removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the second dielectric layer and the nanodots can be removed with an isotropic etch selective to the second dielectric layer.

Abstract translation: 一种制造存储单元的方法，包括在第一介电层上形成纳米点，并在纳米点上形成第二介电层，其中第二介电层包裹纳米点。 此外，在第二介电层上形成隔间电介质层。 为了形成存储器单元的侧壁，间隔电介质层的一部分和第二电介质层的一部分用干蚀刻去除，其中侧壁包括已经沉积纳米点的位置。 在侧壁上形成间隔层以覆盖已经沉积纳米点的位置，并且可以用对第二介电层选择性的各向同性蚀刻去除第二介电层和纳米点的剩余部分。

公开(公告)号：US20100264482A1

公开(公告)日：2010-10-21

申请号：US12829904

申请日：2010-07-02

Applicant: Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

Inventor： Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

IPC: H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/513

Abstract: Memory cells including a control gate, a charge trapping material, and a charge blocking material between the control gate and the charge trapping material. The charge blocking material is configured to allow for erasure of the memory cell by enhanced F-N tunneling of holes from the control gate to the charge trapping material.

Abstract translation: 存储单元包括控制栅极，电荷捕获材料和控制栅极与电荷捕获材料之间的电荷阻挡材料。 电荷阻挡材料被配置为允许通过从控制栅极到电荷捕获材料的孔的增强的F-N隧穿来擦除存储器单元。

公开(公告)号：US07749848B2

公开(公告)日：2010-07-06

申请号：US11900595

申请日：2007-09-12

Applicant: Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

Inventor： Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

IPC: H01L21/336

CPC classification number: H01L29/792 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/513

Abstract: Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate memory cells in NOR or NAND memory architectures that allow for direct tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory cells of the present invention also allow multiple bit storage in a single memory cell, and allow for programming and erase with reduced voltages. A positive voltage erase process via hole tunneling is also provided.

Abstract translation: 描述了非易失性存储器件和阵列，其有助于在NOR或NAND存储器架构中的浮动栅极存储器单元中使用具有非对称隧道势垒的带隙工程化栅极堆叠，这允许直接隧道编程和用电子和空穴擦除，同时保持 高电荷阻挡屏障和深载体捕获位点，具有良好的电荷保留性。 直接隧道编程和擦除功能可以减少高能量载体对栅极堆叠和晶格的损害，减少写入疲劳和泄漏问题，并增强器件寿命。 本发明的存储器单元还允许在单个存储器单元中进行多位存储，并允许以降低的电压进行编程和擦除。 还提供了正电压擦除处理通孔隧穿。

公开(公告)号：US07745283B2

公开(公告)日：2010-06-29

申请号：US11023719

申请日：2004-12-28

Applicant: Kirk D. Prall

Inventor： Kirk D. Prall

IPC: H01L21/336

CPC classification number: H01L29/0847 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/66643 ,  H01L29/7839 ,  H01L29/7885 ,  H01L29/792

Abstract: A method of forming a memory transistor includes providing a substrate comprising semiconductive material and forming spaced-apart source/drain structures. At least one of the source/drain structures forms a Schottky contact to the semiconductive material. The method also includes forming a memory gate between the spaced-apart source/drain structures and forming a control gate disposed operatively over the memory gate.

Abstract translation: 形成存储晶体管的方法包括提供包括半导体材料并形成间隔开的源极/漏极结构的衬底。 源极/漏极结构中的至少一个与半导体材料形成肖特基接触。 该方法还包括在间隔开的源极/漏极结构之间形成存储栅极，并形成可操作地设置在存储器栅极上的控制栅极。

公开(公告)号：US07560769B2

公开(公告)日：2009-07-14

申请号：US11498523

申请日：2006-08-03

Applicant: Gurtej S. Sandhu ,  Kirk D. Prall

Inventor： Gurtej S. Sandhu ,  Kirk D. Prall

IPC: H01L29/788

CPC classification number: H01L29/7881 ,  B82Y10/00 ,  G11C16/0408 ,  G11C2216/06 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/513

Abstract: A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming a second dielectric layer over the nanodots, where the second dielectric layer encases the nanodots. In addition, an intergate dielectric layer is formed over the second dielectric layer. To form sidewalls of the memory cell, a portion of the intergate dielectric layer and a portion of the second dielectric layer are removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the second dielectric layer and the nanodots can be removed with an isotropic etch selective to the second dielectric layer.

Abstract translation: 一种制造存储单元的方法，包括在第一介电层上形成纳米点，并在纳米点上形成第二介电层，其中第二介电层包裹纳米点。 此外，在第二介电层上形成隔间电介质层。 为了形成存储器单元的侧壁，间隔电介质层的一部分和第二电介质层的一部分用干蚀刻去除，其中侧壁包括已经沉积纳米点的位置。 在侧壁上形成间隔层以覆盖已经沉积纳米点的位置，并且可以用对第二介电层选择性的各向同性蚀刻去除第二介电层和纳米点的剩余部分。

公开(公告)号：US20080186777A1

公开(公告)日：2008-08-07

申请号：US11703487

申请日：2007-02-07

Applicant: Lyle D. Jones ,  Roger W. Lindsay ,  Kirk D. Prall

Inventor： Lyle D. Jones ,  Roger W. Lindsay ,  Kirk D. Prall

IPC: G11C11/34 ,  H01L21/8239

CPC classification number: H01L27/115 ,  G11C5/02 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11524

Abstract: A relaxed metal pitch architecture may include a bit line and a first active area string and a second active area string. The bit line may be directly coupled to the first active area string and to the second active area string. The relaxed metal pitch architecture may be applied to a non-volatile memory structure.

Abstract translation: 轻松的金属间距结构可以包括位线和第一有效区域串和第二有效区域串。 位线可以直接耦合到第一有效区域串和第二有效区域串。 轻松的金属间距结构可以应用于非易失性存储器结构。

公开(公告)号：US20080057639A1

公开(公告)日：2008-03-06

申请号：US11512781

申请日：2006-08-29

Applicant: Gurtej S. Sandhu ,  Kirk D. Prall

Inventor： Gurtej S. Sandhu ,  Kirk D. Prall

IPC: H01L21/8244

CPC classification number: H01L27/115 ,  H01L21/28273 ,  H01L27/11521

Abstract: Some embodiments include methods of forming flash memory cells and semiconductor constructions, and some embodiments include semiconductor constructions. Some embodiments may include a method in which a semiconductor substrate is provided to have a plurality of active area locations. Floating gates are formed over the active area locations, with the floating gates having widths that are entirely sub-lithographic. Adjacent floating gates are spaced from one another by gaps. Dielectric material and control gate material are formed over the floating gates and within the gaps. Some embodiments may include a construction in which a pair of adjacent floating gates are over a pair of adjacent active areas, with the floating gates being spaced from one another by a distance which is greater than a distance that the active areas are spaced from one another.

Abstract translation: 一些实施例包括形成快闪存储器单元和半导体结构的方法，并且一些实施例包括半导体结构。 一些实施例可以包括其中提供半导体衬底以具有多个有效区域位置的方法。 浮动栅极形成在有源区位置上，浮栅具有完全亚光刻的宽度。 相邻的浮动门通过间隙彼此间隔开。 电介质材料和控制栅极材料形成在浮动栅极和间隙内。 一些实施例可以包括其中一对相邻浮动栅极在一对相邻有效区域之上的结构，其中浮动栅极彼此间隔一定距离，该距离大于有效区域彼此间隔开的距离 。