Method of forming a transistor having a low-resistance gate electrode
    62.
    发明授权
    Method of forming a transistor having a low-resistance gate electrode 有权
    形成具有低电阻栅电极的晶体管的方法

    公开(公告)号:US06268257B1

    公开(公告)日:2001-07-31

    申请号:US09557714

    申请日:2000-04-25

    CPC classification number: H01L29/66507 H01L21/28247 H01L29/6659

    Abstract: A method is disclosed in which a low-resistance portion of the gate electrode of a transistor is formed independently of the formation of low-resistance portions in the drain and source regions. Accordingly, the device features a thick low-resistance portion in the gate electrode, for example, a thick gate silicide for supporting low gate delays by minimizing the gate resistance, and a thin low-resistance portion in the drain and source in order to meet the requirements for shallow junction integration. Moreover, a transistor is disclosed having a low-resistance gate electrode portion, the composition of which is different from the low-resistance portion of the drain and source.

    Abstract translation: 公开了一种方法,其中晶体管的栅电极的低电阻部分形成为独立于在漏极和源极区域中形成低电阻部分。 因此,该器件在栅电极中具有厚的低电阻部分,例如,通过最小化栅极电阻来支持低栅极延迟的厚栅极硅化物,以及漏极和源极中的薄的低电阻部分,以便满足 浅结合整合的要求。 此外,公开了一种具有低电阻栅极电极部分的晶体管,其组成不同于漏极和源极的低电阻部分。

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