公开(公告)号：US09589191B2

公开(公告)日：2017-03-07

申请号：US14000107

申请日：2012-02-17

Applicant: Marko Stefanovic ,  Rolf-Stephan Badura ,  Jan Karsch

Inventor： Marko Stefanovic ,  Rolf-Stephan Badura ,  Jan Karsch

IPC: G06K9/32 ,  G06K9/00 ,  G08G1/01 ,  G06T7/20 ,  G08B13/196

CPC classification number: G06K9/00771 ,  G06T7/20 ,  G06T2207/30241 ,  G08B13/19608 ,  G08G1/0116 ,  G08G1/0133

Abstract: The invention relates to a method for evaluating a plurality of chronologically staggered images, said method comprising the following steps: detecting a plurality of objects in a first image and storing each of the plurality of objects as tracks with a first capture time and/or a first capture location, preferably in a track list, detecting a plurality of objects in further images and identifying each of the detected objects as an object assigned to the respective stored track, wherein the respective track is updated by the current position of the identified object and, in the respective further images, objects detected for the first time are stored with assigned tracks, and wherein a covered path length, a distance and/or a time difference from the first capture time is determined as a capture period for each of the objects or tracks, wherein the path length, the distance and/or the capture period are compared with a respective predefined threshold value, and wherein the objects or tracks are classified according to the result of the comparison as objects or tracks to be taken into consideration or as objects or tracks not to be taken into consideration, wherein a number of stored tracks is determined for at least one of the images.

Abstract translation: 本发明涉及一种用于评估多个按时间顺序的交错图像的方法，所述方法包括以下步骤：检测第一图像中的多个对象并将多个对象中的每一个存储为具有第一捕获时间的轨迹和/或 第一捕获位置，优选地在轨道列表中，在另外的图像中检测多个对象，并将每个检测到的对象识别为分配给相应存储的轨道的对象，其中相应的轨道被所识别的对象的当前位置更新，以及 在相应的另外的图像中，第一次检测到的对象被存储有分配的轨迹，并且其中将覆盖的路径长度，距离和/或与第一捕获时间的时间差确定为每个对象的捕获周期 或轨道，其中路径长度，距离和/或捕获周期与相应的预定阈值进行比较，并且其中对象或t 根据比较的结果将机架分类为要考虑的对象或轨道或不被考虑的对象或轨道，其中为至少一个图像确定多个存储的轨道。

公开(公告)号：US08846513B2

公开(公告)日：2014-09-30

申请号：US13241915

申请日：2011-09-23

Applicant: Peter Baars ,  Richard Carter ,  Rolf Stephan

Inventor： Peter Baars ,  Richard Carter ,  Rolf Stephan

IPC: H01L21/3205 ,  H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/28518 ,  H01L21/76814 ,  H01L29/66545 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: When forming self-aligned contact elements in sophisticated semiconductor devices in which high-k metal gate electrode structures are to be provided on the basis of a replacement gate approach, the self-aligned contact openings are filled with an appropriate fill material, such as polysilicon, while the gate electrode structures are provided on the basis of a placeholder material that can be removed with high selectivity with respect to the sacrificial fill material. In this manner, the high-k metal gate electrode structures may be completed prior to actually filling the contact openings with an appropriate contact material after the removal of the sacrificial fill material. In one illustrative embodiment, the placeholder material of the gate electrode structures is provided in the form of a silicon/germanium material.

Abstract translation: 当在基于更换栅极方法的高k金属栅电极结构的复杂半导体器件中形成自对准接触元件时，自对准接触开口用适当的填充材料填充，例如多晶硅 而栅电极结构基于可相对于牺牲填充材料以高选择性去除的占位符材料提供。 以这种方式，高k金属栅电极结构可以在去除牺牲填充材料之前用适当的接触材料实际填充接触开口之前完成。 在一个说明性实施例中，栅电极结构的占位符材料以硅/锗材料的形式提供。

公开(公告)号：US20140037141A1

公开(公告)日：2014-02-06

申请号：US14000107

申请日：2012-02-17

Applicant: Marko Stefanovic ,  Rolf-Stephan Badura ,  Jan Karsch

Inventor： Marko Stefanovic ,  Rolf-Stephan Badura ,  Jan Karsch

IPC: G06K9/00

CPC classification number: G06K9/00771 ,  G06T7/20 ,  G06T2207/30241 ,  G08B13/19608 ,  G08G1/0116 ,  G08G1/0133

Abstract: The invention relates to a method for evaluating a plurality of chronologically staggered images, said method comprising the following steps: detecting a plurality of objects in a first image and storing each of the plurality of objects as tracks with a first capture time and/or a first capture location, preferably in a track list, detecting a plurality of objects in further images and identifying each of the detected objects as an object assigned to the respective stored track, wherein the respective track is updated by the current position of the identified object and, in the respective further images, objects detected for the first time are stored with assigned tracks, and wherein a covered path length, a distance and/or a time difference from the first capture time is determined as a capture period for each of the objects or tracks, wherein the path length, the distance and/or the capture period are compared with a respective predefined threshold value, and wherein the objects or tracks are classified according to the result of the comparison as objects or tracks to be taken into consideration or as objects or tracks not to be taken into consideration, wherein a number of stored tracks is determined for at least one of the images.

Abstract translation: 本发明涉及一种用于评估多个按时间顺序的交错图像的方法，所述方法包括以下步骤：检测第一图像中的多个对象并将多个对象中的每一个存储为具有第一捕获时间的轨迹和/或 第一捕获位置，优选地在轨道列表中，在另外的图像中检测多个对象，并将每个检测到的对象识别为分配给相应存储的轨道的对象，其中相应的轨道被所识别的对象的当前位置更新，以及 在相应的另外的图像中，第一次检测到的对象被存储有分配的轨迹，并且其中将覆盖的路径长度，距离和/或与第一捕获时间的时间差确定为每个对象的捕获周期 或轨道，其中路径长度，距离和/或捕获周期与相应的预定阈值进行比较，并且其中对象或t 根据比较的结果将机架分类为要考虑的对象或轨道或不被考虑的对象或轨道，其中为至少一个图像确定多个存储的轨道。

公开(公告)号：US20130115773A1

公开(公告)日：2013-05-09

申请号：US13289122

申请日：2011-11-04

Applicant: Rohit Pal ,  Rolf Stephan ,  Andreas Ott

Inventor： Rohit Pal ,  Rolf Stephan ,  Andreas Ott

IPC: H01L21/311

CPC classification number: H01L21/3105 ,  H01L21/31155 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L29/66545 ,  H01L29/7833

Abstract: When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, pronounced loss of the interlayer dielectric material may be avoided by inserting at least one surface modification process, for instance in the form of a nitridation process. In this manner, leakage paths caused by metal residues formed in the interlayer dielectric material may be significantly reduced.

Abstract translation: 当基于替代栅极方法形成复杂的高k金属栅电极结构时，可以通过插入至少一个表面改性工艺（例如以氮化工艺的形式）来避免层间绝缘材料的显着损失。 以这种方式，可以显着地减少由层间电介质材料中形成的金属残留物引起的泄漏路径。

公开(公告)号：US20100203698A1

公开(公告)日：2010-08-12

申请号：US12763324

申请日：2010-04-20

Applicant: Frank Wirbeleit ,  Rolf Stephan ,  Manfred Horstmann

Inventor： Frank Wirbeleit ,  Rolf Stephan ,  Manfred Horstmann

IPC: H01L21/336

CPC classification number: H01L21/28123 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate.

Abstract translation: 形成半导体结构的方法包括提供半导体衬底。 在衬底上形成特征。 该特征在横向方向上基本上是均匀的。 执行适于将第一掺杂剂离子引入邻近该特征的衬底的至少一部分中的第一离子注入工艺。 横向的特征长度减小。 在特征的长度减小之后，执行适于将第二掺杂剂离子引入邻近该特征的衬底的至少一部分中的第二离子注入工艺。 该特征可以是要形成在半导体衬底上的场效应晶体管的栅电极。

公开(公告)号：US07629211B2

公开(公告)日：2009-12-08

申请号：US11684211

申请日：2007-03-09

Applicant: Sven Beyer ,  Thorsten Kammler ,  Rolf Stephan ,  Manfred Horstmann

Inventor： Sven Beyer ,  Thorsten Kammler ,  Rolf Stephan ,  Manfred Horstmann

IPC: H01L21/331 ,  H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method of forming a field effect transistor comprises providing a semiconductor substrate, a gate electrode being formed over the semiconductor substrate. At least one cavity is formed adjacent the gate electrode. A strain-creating element is formed in the at least one cavity. The strain-creating element comprises a compound material comprising a first chemical element and a second chemical element. A first concentration ratio between a concentration of the first chemical element in a first portion of the strain-creating element and a concentration of the second chemical element in the first portion of the strain-creating element is different from a second concentration ratio between a concentration of the first chemical element in a second portion of the strain-creating element and a concentration of the second chemical element in the second strain-creating element.

Abstract translation: 形成场效应晶体管的方法包括提供半导体衬底，栅电极形成在半导体衬底上。 在栅电极附近形成至少一个空腔。 应变产生元件形成在至少一个空腔中。 应变产生元件包括包含第一化学元素和第二化学元素的复合材料。 应变产生元件的第一部分中的第一化学元素的浓度与应变产生元件的第一部分中的第二化学元素的浓度之间的第一浓度比不同于第二浓度比， 的应变产生元件的第二部分中的第一化学元素和第二应变产生元件中的第二化学元素的浓度。

公开(公告)号：US07605045B2

公开(公告)日：2009-10-20

申请号：US11457300

申请日：2006-07-13

Applicant: Igor Peidous ,  Patrick Press ,  Rolf Stephan

Inventor： Igor Peidous ,  Patrick Press ,  Rolf Stephan

IPC: H01L21/336

CPC classification number: H01L29/7843 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833

Abstract: Field effect transistors and methods for fabricating field effect transistors are provided. A method, in accordance with an exemplary embodiment of the invention, comprises forming a polycrystalline silicon gate electrode overlying a silicon substrate. The gate electrode has two parallel sidewalls. Two sidewall spacers are fabricated overlying the silicon substrate. Each of the two sidewall spacers has a sidewall that is adjacent to one of the two parallel sidewalls of the gate electrode. A portion of the gate electrode between the two sidewall spacers is removed.

Abstract translation: 提供场效应晶体管和制造场效应晶体管的方法。 根据本发明的示例性实施例的方法包括形成覆盖硅衬底的多晶硅栅电极。 栅电极具有两个平行的侧壁。 在硅衬底上制造两个侧壁间隔物。 两个侧壁间隔物中的每一个具有与栅电极的两个平行侧壁中的一个相邻的侧壁。 去除两个侧壁间隔物之间​​的栅电极的一部分。

公开(公告)号：US20080268625A1

公开(公告)日：2008-10-30

申请号：US12023743

申请日：2008-01-31

Applicant: Thomas Feudel ,  Rolf Stephan ,  Manfred Horstmann

Inventor： Thomas Feudel ,  Rolf Stephan ,  Manfred Horstmann

IPC: H01L21/425

CPC classification number: H01L21/26513 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/84 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7848

Abstract: By combining an anneal process for adjusting the effective channel length and a substantially diffusion-free anneal process performed after a deep drain and source implantation, the vertical extension of the drain and source region may be increased substantially without affecting the previously adjusted channel length. In this manner, in SOI devices, the drain and source regions may extend down to the buried insulating layer, thereby reducing the parasitic capacitance, while the degree of dopant activation and thus series resistance in the extension regions may be improved. Furthermore, less critical process parameters during the anneal process for adjusting the channel length may provide the potential for reducing the lateral dimensions of the transistor devices.

Abstract translation: 通过组合用于调节有效沟道长度的退火工艺和在深漏极和源极注入之后执行的基本上无扩散的退火工艺，可以基本上增加漏极和源极区域的垂直延伸，而不影响先前调节的沟道长度。 以这种方式，在SOI器件中，漏极和源极区域可以向下延伸到掩埋绝缘层，从而减小寄生电容，同时可以改善延伸区域中的掺杂剂激活程度和因此的串联电阻。 此外，在用于调整沟道长度的退火工艺期间较不重要的工艺参数可以为降低晶体管器件的横向尺寸提供潜力。

公开(公告)号：US20080242040A1

公开(公告)日：2008-10-02

申请号：US11942400

申请日：2007-11-19

Applicant: Frank Wirbeleit ,  Rolf Stephan ,  Manfred Horstmann

Inventor： Frank Wirbeleit ,  Rolf Stephan ,  Manfred Horstmann

IPC: H01L21/336

CPC classification number: H01L21/28123 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate.

Abstract translation: 形成半导体结构的方法包括提供半导体衬底。 在衬底上形成特征。 该特征在横向上基本上是均匀的。 执行适于将第一掺杂剂离子引入邻近该特征的衬底的至少一部分中的第一离子注入工艺。 横向的特征长度减小。 在特征的长度减小之后，执行适于将第二掺杂剂离子引入邻近该特征的衬底的至少一部分中的第二离子注入工艺。 该特征可以是要形成在半导体衬底上的场效应晶体管的栅电极。

公开(公告)号：US07325224B2

公开(公告)日：2008-01-29

申请号：US10987427

申请日：2004-11-12

Applicant: Rolf Seltmann ,  Heiko Wagner ,  Rolf Stephan

Inventor： Rolf Seltmann ,  Heiko Wagner ,  Rolf Stephan

IPC: G06F17/50

CPC classification number: G03F7/70658 ,  G03F7/70558

Abstract: The electrical performance of sub-devices is detected and the corresponding measurement data is used to control a lithography process so as to compensate for any type of process variations during a manufacturing sequence.

Abstract translation: 检测到子器件的电气性能，并且使用相应的测量数据来控制光刻工艺，以补偿制造顺序期间的任何类型的工艺变化。