Method for evaluating a plurality of time-offset pictures, device for evaluating pictures, and monitoring system
    1.
    发明授权
    Method for evaluating a plurality of time-offset pictures, device for evaluating pictures, and monitoring system 有权
    用于评估多个时间偏移图像的方法,用于评估图像的装置和监视系统

    公开(公告)号:US09589191B2

    公开(公告)日:2017-03-07

    申请号:US14000107

    申请日:2012-02-17

    Abstract: The invention relates to a method for evaluating a plurality of chronologically staggered images, said method comprising the following steps: detecting a plurality of objects in a first image and storing each of the plurality of objects as tracks with a first capture time and/or a first capture location, preferably in a track list, detecting a plurality of objects in further images and identifying each of the detected objects as an object assigned to the respective stored track, wherein the respective track is updated by the current position of the identified object and, in the respective further images, objects detected for the first time are stored with assigned tracks, and wherein a covered path length, a distance and/or a time difference from the first capture time is determined as a capture period for each of the objects or tracks, wherein the path length, the distance and/or the capture period are compared with a respective predefined threshold value, and wherein the objects or tracks are classified according to the result of the comparison as objects or tracks to be taken into consideration or as objects or tracks not to be taken into consideration, wherein a number of stored tracks is determined for at least one of the images.

    Abstract translation: 本发明涉及一种用于评估多个按时间顺序的交错图像的方法,所述方法包括以下步骤:检测第一图像中的多个对象并将多个对象中的每一个存储为具有第一捕获时间的轨迹和/或 第一捕获位置,优选地在轨道列表中,在另外的图像中检测多个对象,并将每个检测到的对象识别为分配给相应存储的轨道的对象,其中相应的轨道被所识别的对象的当前位置更新,以及 在相应的另外的图像中,第一次检测到的对象被存储有分配的轨迹,并且其中将覆盖的路径长度,距离和/或与第一捕获时间的时间差确定为每个对象的捕获周期 或轨道,其中路径长度,距离和/或捕获周期与相应的预定阈值进行比较,并且其中对象或t 根据比较的结果将机架分类为要考虑的对象或轨道或不被考虑的对象或轨道,其中为至少一个图像确定多个存储的轨道。

    Semiconductor device comprising replacement gate electrode structures and self-aligned contact elements formed by a late contact fill
    2.
    发明授权
    Semiconductor device comprising replacement gate electrode structures and self-aligned contact elements formed by a late contact fill 有权
    半导体器件包括替代栅电极结构和由后接触填充形成的自对准接触元件

    公开(公告)号:US08846513B2

    公开(公告)日:2014-09-30

    申请号:US13241915

    申请日:2011-09-23

    Abstract: When forming self-aligned contact elements in sophisticated semiconductor devices in which high-k metal gate electrode structures are to be provided on the basis of a replacement gate approach, the self-aligned contact openings are filled with an appropriate fill material, such as polysilicon, while the gate electrode structures are provided on the basis of a placeholder material that can be removed with high selectivity with respect to the sacrificial fill material. In this manner, the high-k metal gate electrode structures may be completed prior to actually filling the contact openings with an appropriate contact material after the removal of the sacrificial fill material. In one illustrative embodiment, the placeholder material of the gate electrode structures is provided in the form of a silicon/germanium material.

    Abstract translation: 当在基于更换栅极方法的高k金属栅电极结构的复杂半导体器件中形成自对准接触元件时,自对准接触开口用适当的填充材料填充,例如多晶硅 而栅电极结构基于可相对于牺牲填充材料以高选择性去除的占位符材料提供。 以这种方式,高k金属栅电极结构可以在去除牺牲填充材料之前用适当的接触材料实际填充接触开口之前完成。 在一个说明性实施例中,栅电极结构的占位符材料以硅/锗材料的形式提供。

    METHOD FOR EVALUATING A PLURALITY OF TIME-OFFSET PICTURES, DEVICE FOR EVALUATING PICTURES, AND MONITORING SYSTEM
    3.
    发明申请
    METHOD FOR EVALUATING A PLURALITY OF TIME-OFFSET PICTURES, DEVICE FOR EVALUATING PICTURES, AND MONITORING SYSTEM 有权
    用于评估大量时间偏移图像的方法,用于评估图像的设备和监视系统

    公开(公告)号:US20140037141A1

    公开(公告)日:2014-02-06

    申请号:US14000107

    申请日:2012-02-17

    Abstract: The invention relates to a method for evaluating a plurality of chronologically staggered images, said method comprising the following steps: detecting a plurality of objects in a first image and storing each of the plurality of objects as tracks with a first capture time and/or a first capture location, preferably in a track list, detecting a plurality of objects in further images and identifying each of the detected objects as an object assigned to the respective stored track, wherein the respective track is updated by the current position of the identified object and, in the respective further images, objects detected for the first time are stored with assigned tracks, and wherein a covered path length, a distance and/or a time difference from the first capture time is determined as a capture period for each of the objects or tracks, wherein the path length, the distance and/or the capture period are compared with a respective predefined threshold value, and wherein the objects or tracks are classified according to the result of the comparison as objects or tracks to be taken into consideration or as objects or tracks not to be taken into consideration, wherein a number of stored tracks is determined for at least one of the images.

    Abstract translation: 本发明涉及一种用于评估多个按时间顺序的交错图像的方法,所述方法包括以下步骤:检测第一图像中的多个对象并将多个对象中的每一个存储为具有第一捕获时间的轨迹和/或 第一捕获位置,优选地在轨道列表中,在另外的图像中检测多个对象,并将每个检测到的对象识别为分配给相应存储的轨道的对象,其中相应的轨道被所识别的对象的当前位置更新,以及 在相应的另外的图像中,第一次检测到的对象被存储有分配的轨迹,并且其中将覆盖的路径长度,距离和/或与第一捕获时间的时间差确定为每个对象的捕获周期 或轨道,其中路径长度,距离和/或捕获周期与相应的预定阈值进行比较,并且其中对象或t 根据比较的结果将机架分类为要考虑的对象或轨道或不被考虑的对象或轨道,其中为至少一个图像确定多个存储的轨道。

    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE
    5.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE 审中-公开
    形成半导体结构的方法

    公开(公告)号:US20100203698A1

    公开(公告)日:2010-08-12

    申请号:US12763324

    申请日:2010-04-20

    CPC classification number: H01L21/28123 H01L29/66545 H01L29/6659

    Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate.

    Abstract translation: 形成半导体结构的方法包括提供半导体衬底。 在衬底上形成特征。 该特征在横向方向上基本上是均匀的。 执行适于将第一掺杂剂离子引入邻近该特征的衬底的至少一部分中的第一离子注入工艺。 横向的特征长度减小。 在特征的长度减小之后,执行适于将第二掺杂剂离子引入邻近该特征的衬底的至少一部分中的第二离子注入工艺。 该特征可以是要形成在半导体衬底上的场效应晶体管的栅电极。

    Field effect transistor and method of forming a field effect transistor
    6.
    发明授权
    Field effect transistor and method of forming a field effect transistor 有权
    场效应晶体管和形成场效应晶体管的方法

    公开(公告)号:US07629211B2

    公开(公告)日:2009-12-08

    申请号:US11684211

    申请日:2007-03-09

    Abstract: A method of forming a field effect transistor comprises providing a semiconductor substrate, a gate electrode being formed over the semiconductor substrate. At least one cavity is formed adjacent the gate electrode. A strain-creating element is formed in the at least one cavity. The strain-creating element comprises a compound material comprising a first chemical element and a second chemical element. A first concentration ratio between a concentration of the first chemical element in a first portion of the strain-creating element and a concentration of the second chemical element in the first portion of the strain-creating element is different from a second concentration ratio between a concentration of the first chemical element in a second portion of the strain-creating element and a concentration of the second chemical element in the second strain-creating element.

    Abstract translation: 形成场效应晶体管的方法包括提供半导体衬底,栅电极形成在半导体衬底上。 在栅电极附近形成至少一个空腔。 应变产生元件形成在至少一个空腔中。 应变产生元件包括包含第一化学元素和第二化学元素的复合材料。 应变产生元件的第一部分中的第一化学元素的浓度与应变产生元件的第一部分中的第二化学元素的浓度之间的第一浓度比不同于第二浓度比, 的应变产生元件的第二部分中的第一化学元素和第二应变产生元件中的第二化学元素的浓度。

    Field effect transistors and methods for fabricating the same
    7.
    发明授权
    Field effect transistors and methods for fabricating the same 有权
    场效应晶体管及其制造方法

    公开(公告)号:US07605045B2

    公开(公告)日:2009-10-20

    申请号:US11457300

    申请日:2006-07-13

    Abstract: Field effect transistors and methods for fabricating field effect transistors are provided. A method, in accordance with an exemplary embodiment of the invention, comprises forming a polycrystalline silicon gate electrode overlying a silicon substrate. The gate electrode has two parallel sidewalls. Two sidewall spacers are fabricated overlying the silicon substrate. Each of the two sidewall spacers has a sidewall that is adjacent to one of the two parallel sidewalls of the gate electrode. A portion of the gate electrode between the two sidewall spacers is removed.

    Abstract translation: 提供场效应晶体管和制造场效应晶体管的方法。 根据本发明的示例性实施例的方法包括形成覆盖硅衬底的多晶硅栅电极。 栅电极具有两个平行的侧壁。 在硅衬底上制造两个侧壁间隔物。 两个侧壁间隔物中的每一个具有与栅电极的两个平行侧壁中的一个相邻的侧壁。 去除两个侧壁间隔物之间​​的栅电极的一部分。

    ENHANCING TRANSISTOR CHARACTERISTICS BY A LATE DEEP IMPLANTATION IN COMBINATION WITH A DIFFUSION-FREE ANNEAL PROCESS
    8.
    发明申请
    ENHANCING TRANSISTOR CHARACTERISTICS BY A LATE DEEP IMPLANTATION IN COMBINATION WITH A DIFFUSION-FREE ANNEAL PROCESS 有权
    通过最后深度植入与无扩张的方法进行组合来增强晶体管特性

    公开(公告)号:US20080268625A1

    公开(公告)日:2008-10-30

    申请号:US12023743

    申请日:2008-01-31

    Abstract: By combining an anneal process for adjusting the effective channel length and a substantially diffusion-free anneal process performed after a deep drain and source implantation, the vertical extension of the drain and source region may be increased substantially without affecting the previously adjusted channel length. In this manner, in SOI devices, the drain and source regions may extend down to the buried insulating layer, thereby reducing the parasitic capacitance, while the degree of dopant activation and thus series resistance in the extension regions may be improved. Furthermore, less critical process parameters during the anneal process for adjusting the channel length may provide the potential for reducing the lateral dimensions of the transistor devices.

    Abstract translation: 通过组合用于调节有效沟道长度的退火工艺和在深漏极和源极注入之后执行的基本上无扩散的退火工艺,可以基本上增加漏极和源极区域的垂直延伸,而不影响先前调节的沟道长度。 以这种方式,在SOI器件中,漏极和源极区域可以向下延伸到掩埋绝缘层,从而减小寄生电容,同时可以改善延伸区域中的掺杂剂激活程度和因此的串联电阻。 此外,在用于调整沟道长度的退火工艺期间较不重要的工艺参数可以为降低晶体管器件的横向尺寸提供潜力。

    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE
    9.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE 有权
    形成半导体结构的方法

    公开(公告)号:US20080242040A1

    公开(公告)日:2008-10-02

    申请号:US11942400

    申请日:2007-11-19

    CPC classification number: H01L21/28123 H01L29/66545 H01L29/6659

    Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate.

    Abstract translation: 形成半导体结构的方法包括提供半导体衬底。 在衬底上形成特征。 该特征在横向上基本上是均匀的。 执行适于将第一掺杂剂离子引入邻近该特征的衬底的至少一部分中的第一离子注入工艺。 横向的特征长度减小。 在特征的长度减小之后,执行适于将第二掺杂剂离子引入邻近该特征的衬底的至少一部分中的第二离子注入工艺。 该特征可以是要形成在半导体衬底上的场效应晶体管的栅电极。

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