Abstract:
The invention relates to a method for evaluating a plurality of chronologically staggered images, said method comprising the following steps: detecting a plurality of objects in a first image and storing each of the plurality of objects as tracks with a first capture time and/or a first capture location, preferably in a track list, detecting a plurality of objects in further images and identifying each of the detected objects as an object assigned to the respective stored track, wherein the respective track is updated by the current position of the identified object and, in the respective further images, objects detected for the first time are stored with assigned tracks, and wherein a covered path length, a distance and/or a time difference from the first capture time is determined as a capture period for each of the objects or tracks, wherein the path length, the distance and/or the capture period are compared with a respective predefined threshold value, and wherein the objects or tracks are classified according to the result of the comparison as objects or tracks to be taken into consideration or as objects or tracks not to be taken into consideration, wherein a number of stored tracks is determined for at least one of the images.
Abstract:
When forming self-aligned contact elements in sophisticated semiconductor devices in which high-k metal gate electrode structures are to be provided on the basis of a replacement gate approach, the self-aligned contact openings are filled with an appropriate fill material, such as polysilicon, while the gate electrode structures are provided on the basis of a placeholder material that can be removed with high selectivity with respect to the sacrificial fill material. In this manner, the high-k metal gate electrode structures may be completed prior to actually filling the contact openings with an appropriate contact material after the removal of the sacrificial fill material. In one illustrative embodiment, the placeholder material of the gate electrode structures is provided in the form of a silicon/germanium material.
Abstract:
The invention relates to a method for evaluating a plurality of chronologically staggered images, said method comprising the following steps: detecting a plurality of objects in a first image and storing each of the plurality of objects as tracks with a first capture time and/or a first capture location, preferably in a track list, detecting a plurality of objects in further images and identifying each of the detected objects as an object assigned to the respective stored track, wherein the respective track is updated by the current position of the identified object and, in the respective further images, objects detected for the first time are stored with assigned tracks, and wherein a covered path length, a distance and/or a time difference from the first capture time is determined as a capture period for each of the objects or tracks, wherein the path length, the distance and/or the capture period are compared with a respective predefined threshold value, and wherein the objects or tracks are classified according to the result of the comparison as objects or tracks to be taken into consideration or as objects or tracks not to be taken into consideration, wherein a number of stored tracks is determined for at least one of the images.
Abstract:
When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, pronounced loss of the interlayer dielectric material may be avoided by inserting at least one surface modification process, for instance in the form of a nitridation process. In this manner, leakage paths caused by metal residues formed in the interlayer dielectric material may be significantly reduced.
Abstract:
A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate.
Abstract:
A method of forming a field effect transistor comprises providing a semiconductor substrate, a gate electrode being formed over the semiconductor substrate. At least one cavity is formed adjacent the gate electrode. A strain-creating element is formed in the at least one cavity. The strain-creating element comprises a compound material comprising a first chemical element and a second chemical element. A first concentration ratio between a concentration of the first chemical element in a first portion of the strain-creating element and a concentration of the second chemical element in the first portion of the strain-creating element is different from a second concentration ratio between a concentration of the first chemical element in a second portion of the strain-creating element and a concentration of the second chemical element in the second strain-creating element.
Abstract:
Field effect transistors and methods for fabricating field effect transistors are provided. A method, in accordance with an exemplary embodiment of the invention, comprises forming a polycrystalline silicon gate electrode overlying a silicon substrate. The gate electrode has two parallel sidewalls. Two sidewall spacers are fabricated overlying the silicon substrate. Each of the two sidewall spacers has a sidewall that is adjacent to one of the two parallel sidewalls of the gate electrode. A portion of the gate electrode between the two sidewall spacers is removed.
Abstract:
By combining an anneal process for adjusting the effective channel length and a substantially diffusion-free anneal process performed after a deep drain and source implantation, the vertical extension of the drain and source region may be increased substantially without affecting the previously adjusted channel length. In this manner, in SOI devices, the drain and source regions may extend down to the buried insulating layer, thereby reducing the parasitic capacitance, while the degree of dopant activation and thus series resistance in the extension regions may be improved. Furthermore, less critical process parameters during the anneal process for adjusting the channel length may provide the potential for reducing the lateral dimensions of the transistor devices.
Abstract:
A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate.
Abstract:
The electrical performance of sub-devices is detected and the corresponding measurement data is used to control a lithography process so as to compensate for any type of process variations during a manufacturing sequence.