CELLULOSIC PROCESSING TRAIT DEVELOPMENT USING A THERMOREGULATED, INTEIN-MODIFIED XYLANASE
    1.
    发明申请
    CELLULOSIC PROCESSING TRAIT DEVELOPMENT USING A THERMOREGULATED, INTEIN-MODIFIED XYLANASE 有权
    使用加热改性的XYLANASE进行的细胞处理过程开发

    公开(公告)号:US20130203125A1

    公开(公告)日:2013-08-08

    申请号:US13818928

    申请日:2011-08-23

    Abstract: In planta consolidated bioprocessing has the advantages of decreasing biomass pretreatment costs, utilizing excess plant protein production capacity for enzyme production, and decreasing mass transfer resistance of enzyme diffusion to its substrate. However, in planta expression of cell wall degrading (CWD) enzymes often leads to detrimental plant phenotypes that impact crop yield. To provide in planta CWD enzyme activity without any adverse phenotype, a thermostable xylanase, XynB (EC 3.2.1.8), was engineered with a thermoregulated intein, Tth-HB27 DnaE-1 (Tth intein), that controls its hydrolytic activity through conditional intein splicing. Maize plants expressing the heat inducible Tth intein-modified XynB developed normally, yet possessed enhanced post harvest glucose production from dried corn stover. Expression of CWD enzymes as dormant, intein-modified proteins that can be activated by heat treatment after harvest provides the basis for developing a novel cellulosic processing trait in plants.

    Abstract translation: 在植物中,综合生物处理具有降低生物量预处理成本,利用植物蛋白生产过剩的酶生产能力,降低酶扩散对其底物的传质阻力的优点。 然而,在植物表达的细胞壁降解(CWD)酶通常导致有害的植物表型影响作物产量。 为了在没有任何不良表型的情况下提供植物CWD酶活性,用热调节的内含肽Tth-HB27DnaE-1(第T个内含肽)设计热稳定的木聚糖酶XynB(EC 3.2.1.8),其通过条件内含肽来控制其水解活性 拼接。 表达热诱导性Tth内蛋白修饰的XynB的玉米植物正常发育,但是从干燥的玉米秸秆中获得增强的后收获葡萄糖产量。 CWD酶作为休眠后的内含肽修饰蛋白质的表达,可以在收获后通过热处理活化,为开发植物中新型纤维素加工性状提供依据。

    Method of forming sidewall spacers
    5.
    发明授权
    Method of forming sidewall spacers 有权
    形成侧墙的方法

    公开(公告)号:US07316975B2

    公开(公告)日:2008-01-08

    申请号:US11177216

    申请日:2005-07-08

    CPC classification number: H01L21/823468

    Abstract: A substrate comprising a first transistor element and a second transistor element is provided. A layer of a material is deposited over the first transistor element and the second transistor element. A portion of the layer of material is modified, which may be done, e.g., by irradiating the portion with ions or performing an isotropic etching process to reduce its thickness. An etching process adapted to remove the modified portion of the layer of material more quickly than an unmodified portion of the layer located over the second transistor element is performed.

    Abstract translation: 提供了包括第一晶体管元件和第二晶体管元件的衬底。 一层材料沉积在第一晶体管元件和第二晶体管元件上。 材料层的一部分被修饰,其可以例如通过用离子照射部分或执行各向同性蚀刻工艺来实现,以减小其厚度。 执行适于比位于第二晶体管元件上方的层的未修改部分更快地去除材料层的修饰部分的蚀刻工艺。

    Sidewall spacer based fet alignment technology

    公开(公告)号:US06593197B2

    公开(公告)日:2003-07-15

    申请号:US09811733

    申请日:2001-03-19

    CPC classification number: H01L29/6659

    Abstract: This invention provides methods of forming a field-effect transistor in an integrated circuit using self-aligning technology on the basis of a sidewall spacer masking procedure, both for defining the device isolation features and the source and drain regions. The active region is defined after patterning the gate electrode by means of deposition and etch processes instead of overlay alignment technique. Thus, the present invention enables an increase of the integration density of semiconductor devices, a minimization of the parasitic capacitances in field-effect transistor devices, and a quicker manufacturing process.

    Method of forming a transistor having a low-resistance gate electrode
    9.
    发明授权
    Method of forming a transistor having a low-resistance gate electrode 有权
    形成具有低电阻栅电极的晶体管的方法

    公开(公告)号:US06268257B1

    公开(公告)日:2001-07-31

    申请号:US09557714

    申请日:2000-04-25

    CPC classification number: H01L29/66507 H01L21/28247 H01L29/6659

    Abstract: A method is disclosed in which a low-resistance portion of the gate electrode of a transistor is formed independently of the formation of low-resistance portions in the drain and source regions. Accordingly, the device features a thick low-resistance portion in the gate electrode, for example, a thick gate silicide for supporting low gate delays by minimizing the gate resistance, and a thin low-resistance portion in the drain and source in order to meet the requirements for shallow junction integration. Moreover, a transistor is disclosed having a low-resistance gate electrode portion, the composition of which is different from the low-resistance portion of the drain and source.

    Abstract translation: 公开了一种方法,其中晶体管的栅电极的低电阻部分形成为独立于在漏极和源极区域中形成低电阻部分。 因此,该器件在栅电极中具有厚的低电阻部分,例如,通过最小化栅极电阻来支持低栅极延迟的厚栅极硅化物,以及漏极和源极中的薄的低电阻部分,以便满足 浅结合整合的要求。 此外,公开了一种具有低电阻栅极电极部分的晶体管,其组成不同于漏极和源极的低电阻部分。

    Acceleration sensor with cantilevered bending beam
    10.
    发明授权
    Acceleration sensor with cantilevered bending beam 失效
    带悬臂梁的加速度传感器

    公开(公告)号:US5027657A

    公开(公告)日:1991-07-02

    申请号:US445235

    申请日:1989-12-01

    CPC classification number: G01P1/003 G01P15/08 G01P15/105 Y10S73/03

    Abstract: An acceleration sensor essentially consists of a cantilevered laterally bending beam arranged in a housing. Because of its mass inertia the bending beam is deflectable relative to the sensor housing in the plane of the acceleration to be measured. The bending beam has the design of a thin resilient strip which is wide relative to its thickness and is made of amorphous metal. The bending beam may have a one-layer or a multi-layer structure. In case of a multi-layer structure, the friction between the individual strips, causes the vibration to be damped. A small air gap between the walls of a closed housing and the bending beam additionally brings about an air damping of the bending beam's vibrations.

    Abstract translation: 加速度传感器基本上由布置在壳体中的悬臂式横向弯曲梁组成。 由于其质量惯性,弯曲梁相对于传感器外壳在待测加速度平面内是可偏转的。 弯曲梁具有相对于其厚度宽的薄弹性带的设计,并且由非晶金属制成。 弯曲梁可以具有一层或多层结构。 在多层结构的情况下,单个条带之间的摩擦导致振动被阻尼。 封闭壳体的壁与弯曲梁之间的小空气间隙又引起弯曲梁振动的空气阻尼。

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