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公开(公告)号：US20230161484A1
公开(公告)日：2023-05-25
申请号：US17989389
申请日：2022-11-17
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Loic Pallardy , Michel Jaouen
IPC: G06F3/06
CPC classification number: G06F3/0622 , G06F3/0655 , G06F3/0673
Abstract: In embodiments, a system includes a first and a second processing unit, a memory, and a firewall device. The first processing unit operates in a secure mode and generates memory access requests having a secure level. The second processing unit operates in a non-secure mode and generates memory access requests having a non-secure level. The memory includes a first memory area that can be shared between the first and second processing units. The firewall device includes a first firewall circuit with a first configuration authorizing access to the first memory area in the presence of a secure or non-secure level access request. The firewall circuit includes a second configuration prohibiting access to the first memory area in the presence of a secure level access request and authorizing access to the first memory area only in the presence of a non-secure level access request.
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公开(公告)号：US11658576B2
公开(公告)日：2023-05-23
申请号：US17648471
申请日：2022-01-20
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Lionel Cimaz
CPC classification number: H02M3/1582 , H02M1/082 , H02M1/0012 , H02M1/0022
Abstract: An embodiment DC to DC conversion circuit comprises a DC to DC converter and a regulation circuit. The regulation circuit comprises a comparator configured to detect, during a discharge phase of the DC to DC converter, an overshoot period during which an output voltage of the DC to DC converter exceeds a target voltage, and a timer configured to measure a duration of the overshoot period.
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公开(公告)号：US20230153102A1
公开(公告)日：2023-05-18
申请号：US18156550
申请日：2023-01-19
Inventor： Fabien Arrivé , Olivier Leo E. Collart
Abstract: A device includes a memory, a first firmware copy of the device stored in a first position of the memory and a second firmware copy of the device stored in a second position of the memory, where each of the first firmware copy and the second firmware copy includes instructions, when executed by the device, perform an operation of the device; and a first delta copy associated with the first firmware copy. The first delta copy includes instructions that differ from the first firmware copy when executed at the first position and are the same when executed at the second position. The device is configured to receive the first delta copy from an external system and store the first delta copy in the memory.
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公开(公告)号：US20230022755A1
公开(公告)日：2023-01-26
申请号：US17868456
申请日：2022-07-19
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Fabien GREGOIRE
Abstract: A system on chip includes a non-volatile memory and a processor configured to execute an operating system which receives data according to a first communication protocol and program installation software that communicates with the non-volatile memory according to a second communication protocol. The operating system functions to: determine whether data received according to the first communication protocol is program data, make the program data available to the installation software, and inform the installation software that program data has been received. The installation software then stores the program data in the non-volatile memory.
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公开(公告)号：US20220342655A1
公开(公告)日：2022-10-27
申请号：US17660092
申请日：2022-04-21
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Frederic RUELLE
Abstract: According to one aspect, a method adds an additional function to a computer program installed on a microcontroller, the computer program using a table configured to associate an identifier of the additional function with a pointer to a memory address. The method includes the microcontroller obtaining a compiled code of the additional function and an identifier of this additional function, the microcontroller recording the compiled code of the additional function in a section of a memory, and recording in memory a pointer in the table, the pointer being aimed at the address of the memory section in which the compiled code of the additional function is recorded, the pointer being associated in the table with the identifier of the additional function.
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Patent Agency Ranking
公开(公告)号：US11455433B2
公开(公告)日：2022-09-27
申请号：US16579442
申请日：2019-09-23
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Arnaud Rosay , Gerald Lejeune , Jean Nicolas Graux , Olivier Claude LeBreton
Abstract: In one embodiment, a system on chip includes a dynamic voltage and frequency scaling (DVFS) power supply, a secure environment, a non-secure environment, and a power supply management control module. The secure environment is configured to generate a secure instruction defining a permitted operating point of voltage and frequency for the DVFS power supply. The non-secure environment is configured to generate a request to modify the DVFS power supply, where the request to modify includes a voltage-frequency operating point. The power supply management control module is configured to scale the DVFS power supply to the permitted operating point, in response to the request to modify the DVFS power supply.
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公开(公告)号：US20220197828A1
公开(公告)日：2022-06-23
申请号：US17457569
申请日：2021-12-03
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Frederic Ruelle
Abstract: A system includes a processing unit, a memory configured to store at least one first group of instructions and one second group of instructions for execution by the processing unit, the processing unit being configured to sequentially extract from the memory instructions of the first group and instructions of the second group for their execution. The system also includes a controller including a first auxiliary memory configured to store a protection criterion, a comparator configured to compare the storage address of each extracted instruction with the protection criterion, and a control circuit configured to, in response to the storage address meeting the protection criterion, trigger a protection mechanism including at least one prohibition for the processing unit to execute again at least one portion of the instructions of the first group, during the execution of the instructions of the second group.
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公开(公告)号：US20220156217A1
公开(公告)日：2022-05-19
申请号：US17587954
申请日：2022-01-28
Inventor： Loic Pallardy , Nicolas Saux
IPC: G06F13/40 , G06F13/362
Abstract: A system including a first port configured to simultaneously couple with a first device and a second device; and a management circuit configured to route a data signal received from a first controller to the first device in response to receiving a first-device direction from the first controller and route the data signal received from the first controller to the second device in response to receiving a second-device direction from the first controller unless an override condition for the management circuit is satisfied.
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公开(公告)号：US20220140734A1
公开(公告)日：2022-05-05
申请号：US17648471
申请日：2022-01-20
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Lionel Cimaz
Abstract: An embodiment DC to DC conversion circuit comprises a DC to DC converter and a regulation circuit. The regulation circuit comprises a comparator configured to detect, during a discharge phase of the DC to DC converter, an overshoot period during which an output voltage of the DC to DC converter exceeds a target voltage, and a timer configured to measure a duration of the overshoot period.
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公开(公告)号：US11303199B2
公开(公告)日：2022-04-12
申请号：US16854483
申请日：2020-04-21
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Lionel Cimaz
Abstract: A method for limiting an input or output current of a DC-DC converter and a current limiting circuit are disclosed. In an embodiment a method for limiting an input or output current of a DC to DC converter includes storing a first value representative of a level of an output voltage of the DC to DC converter in response to the input or output current exceeding or falling below a first threshold and modifying a control signal based on the first value.
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