公开(公告)号：US20120097989A1

公开(公告)日：2012-04-26

申请号：US13188338

申请日：2011-07-21

Applicant: Sung-Soo Lee ,  Gwan-Hyoung Lee

Inventor： Sung-Soo Lee ,  Gwan-Hyoung Lee

IPC: H01L33/08

CPC classification number: H01L51/5278 ,  H01L27/3209 ,  H01L51/504

Abstract: An organic light emitting diode device comprises a first electrode, a second electrode facing the first electrode, a first light emitting unit and a second light emitting unit positioned between the first electrode and the second electrode, a charge generation layer positioned between the first light emitting unit and the second light emitting unit, and a charge balance layer positioned adjacent to charge generation layer and including a lithium-containing compound.

Abstract translation: 有机发光二极管装置包括第一电极，面向第一电极的第二电极，位于第一电极和第二电极之间的第一发光单元和第二发光单元，位于第一发光二极管 单元和第二发光单元，以及与电荷产生层相邻并且包含含锂化合物的电荷平衡层。

公开(公告)号：US20110240967A1

公开(公告)日：2011-10-06

申请号：US13064532

申请日：2011-03-30

Applicant: Young-Shin Lee ,  Jae-Kook Ha ,  Sung-Soo Lee

Inventor： Young-Shin Lee ,  Jae-Kook Ha ,  Sung-Soo Lee

IPC: H01L51/52

CPC classification number: H01L51/5088 ,  H01L51/5004 ,  H01L2251/552

Abstract: An organic light emitting diode device, including a first electrode, a second electrode facing the first electrode, and a light emitting member disposed between the first electrode and the second electrode, the light emitting member including at least one light emitting unit. At least one of the light emitting units may include a first hole injection layer, a second hole injection layer, a hole transport layer, and an emission layer, and a difference between a HOMO energy level of the first hole injection layer and a LUMO energy level of the second hole injection layer may be smaller than about 0.5 eV.

Abstract translation: 一种有机发光二极管装置，包括第一电极，面对第一电极的第二电极和设置在第一电极和第二电极之间的发光部件，发光部件包括至少一个发光单元。 至少一个发光单元可以包括第一空穴注入层，第二空穴注入层，空穴传输层和发射层，以及第一空穴注入层的HOMO能级与LUMO能量之间的差 第二空穴注入层的电平可以小于约0.5eV。

公开(公告)号：US07990044B2

公开(公告)日：2011-08-02

申请号：US11767700

申请日：2007-06-25

Applicant: Sung-Soo Lee ,  Beohm-Rock Choi ,  Kyong-Tae Park ,  Young-Rok Song ,  Ji-Hye Choi

Inventor： Sung-Soo Lee ,  Beohm-Rock Choi ,  Kyong-Tae Park ,  Young-Rok Song ,  Ji-Hye Choi

IPC: H01J9/44 ,  H01J9/00 ,  G09G3/10 ,  G09G3/32

CPC classification number: H01L27/3244 ,  H01L2251/562

Abstract: The present invention provides an electrical processing apparatus and method for electrically processing a display panel having an organic light-emitting layer. The method for electrically processing a display panel having an organic light-emitting layer includes dividing a light-emitting region of the display panel into a plurality of regions; and applying a voltage to at least one region of the plurality of regions where an amplitude of the voltage exceeds an amplitude of a driving voltage of the display panel. The electrical processing apparatus includes a display panel comprising an organic light-emitting layer, a light emitting region, and a plurality of regions, the plurality of regions being defined by dividing the light emitting region; a jig for holding the display panel; and a current supplying portion, wherein the current supplying portion supplies a current individually to each of the plurality of regions.

Abstract translation: 本发明提供一种电加工具有有机发光层的显示面板的电加工装置和方法。 电化学处理具有有机发光层的显示面板的方法包括将显示面板的发光区域划分为多个区域; 以及对电压的幅度超过显示面板的驱动电压的振幅的多个区域中的至少一个区域施加电压。 电气处理装置包括：显示面板，包括有机发光层，发光区域和多个区域，所述多个区域通过划分发光区域而限定; 夹持显示面板的夹具; 和电流供应部分，其中电流供应部分分别向多个区域中的每个区域提供电流。

公开(公告)号：US07825581B2

公开(公告)日：2010-11-02

申请号：US12121188

申请日：2008-05-15

Applicant: Sung-Soo Lee ,  Jun-Ho Choi ,  Chang-Woong Chu ,  Seong-Min Kim

Inventor： Sung-Soo Lee ,  Jun-Ho Choi ,  Chang-Woong Chu ,  Seong-Min Kim

IPC: H01J1/62 ,  H01J63/04

CPC classification number: H01L51/5265 ,  H01L27/3206 ,  H01L27/3213 ,  H01L27/322 ,  H01L51/5036 ,  H01L51/5215 ,  H01L2251/308 ,  H01L2251/558

Abstract: A method for manufacturing an organic light emitting diode (“OLED”) display which includes first and second pixels each displaying a different color, the method includes: sequentially depositing a first transparent conductive layer and a translucent conductive layer; forming an intermediate first electrode on the second pixel by photolithography and etching of the translucent conductive layer; depositing a second transparent conductive layer on the intermediate first electrode and the first transparent conductive layer; forming a first electrode of the first pixel which includes upper and lower layers on the first pixel and a first electrode of the second pixel which includes a lower first electrode, an intermediate first electrode, and an upper first electrode by photolithography and etching of the second transparent conductive layer and the first transparent conductive layer; forming an emission layer on the first electrodes of the first and second pixels; and forming a second electrode on the emission layer.

Abstract translation: 一种制造有机发光二极管（“OLED”）显示器的方法，其包括每个显示不同颜色的第一和第二像素，所述方法包括：顺序地沉积第一透明导电层和半透明导电层; 通过光刻和半透明导电层的蚀刻在第二像素上形成中间第一电极; 在所述中间第一电极和所述第一透明导电层上沉积第二透明导电层; 形成第一像素的第一电极，其包括第一像素上的上层和下层，以及第二像素的第一电极，其包括下第一电极，中间第一电极和上第一电极，通过光刻和第二像素的蚀刻 透明导电层和第一透明导电层; 在第一和第二像素的第一电极上形成发射层; 以及在所述发射层上形成第二电极。

公开(公告)号：US20100229001A1

公开(公告)日：2010-09-09

申请号：US12711458

申请日：2010-02-24

Applicant: Jung Hoon PARK ,  Sung Soo LEE

Inventor： Jung Hoon PARK ,  Sung Soo LEE

IPC: G06F12/14 ,  H04L9/06

CPC classification number: G11C16/22

Abstract: Disclosed is an operating method of a non-volatile memory device which comprises randomizing data to store the randomized data; erasing the randomized data; and outputting erase data according to information of a flag cell of the non-volatile memory device at a read operation.

Abstract translation: 公开了一种非易失性存储器件的操作方法，其包括随机化数据以存储随机数据; 擦除随机数据; 以及在读取操作时根据所述非易失性存储器件的标志单元的信息输出擦除数据。

公开(公告)号：US20100202204A1

公开(公告)日：2010-08-12

申请号：US12752213

申请日：2010-04-01

Applicant: Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

Inventor： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

IPC: G11C16/04 ,  G11C7/10

CPC classification number: G11C16/0483 ,  G11C16/26

Abstract: In one aspect, a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node.

Abstract translation: 在一个方面，提供一种可在编程模式和读取模式下操作的非易失性存储器件。 存储器件包括存储单元阵列，其包括多个非易失性存储器单元，多个字线和多个位线。 存储器件还包括用于输出从存储器阵列的位线读取的数据的内部数据输出线以及可操作地连接在存储单元阵列的位线和内部数据输出线之间的页缓冲器。 页面缓冲器包括选择性地连接到位线的感测节点，具有选择性地连接到感测节点的锁存节点的锁存电路，将锁存节点的逻辑电压设置为编程模式的锁存器输入路径，以及 读取模式和与锁存器输入路径分离并根据锁存节点的逻辑电压设置为内部日期输出线的逻辑电压的锁存器输出路径。

公开(公告)号：US20100133517A1

公开(公告)日：2010-06-03

申请号：US12437321

申请日：2009-05-07

Applicant: Sung-Hun Lee ,  Jung-Bae Song ,  Sung-Soo Lee

Inventor： Sung-Hun Lee ,  Jung-Bae Song ,  Sung-Soo Lee

IPC: H01L51/52

CPC classification number: H01L51/5052

Abstract: An organic light emitting element and an organic light emitting device including the same is provided. At least one p-type or n-type overdoping layer is formed between two light emitting members forming a p-n junction in the organic light emitting element.

Abstract translation: 提供有机发光元件和包括该有机发光元件的有机发光元件。 在有机发光元件中形成p-n结的两个发光元件之间形成至少一个p型或n型过掺杂层。

公开(公告)号：US20090296494A1

公开(公告)日：2009-12-03

申请号：US12035028

申请日：2008-02-21

Applicant: Sung-Soo LEE ,  Young-Ho LIM ,  Hyun-Chul CHO ,  Dong-Hyuk CHAE

Inventor： Sung-Soo LEE ,  Young-Ho LIM ,  Hyun-Chul CHO ,  Dong-Hyuk CHAE

IPC: G11C7/10

CPC classification number: G11C16/0483 ,  G11C16/26

Abstract: In one aspect a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node.

Abstract translation: 在一个方面，提供可在编程模式和读取模式下操作的非易失性存储器件。 存储器件包括存储单元阵列，其包括多个非易失性存储器单元，多个字线和多个位线。 存储器件还包括用于输出从存储器阵列的位线读取的数据的内部数据输出线以及可操作地连接在存储单元阵列的位线和内部数据输出线之间的页缓冲器。 页面缓冲器包括选择性地连接到位线的感测节点，具有选择性地连接到感测节点的锁存节点的锁存电路，将锁存节点的逻辑电压设置为编程模式的锁存器输入路径，以及 读取模式和与锁存器输入路径分离并根据锁存节点的逻辑电压设置为内部日期输出线的逻辑电压的锁存器输出路径。

公开(公告)号：US07495968B2

公开(公告)日：2009-02-24

申请号：US11317079

申请日：2005-12-27

Applicant: Sung Soo Lee ,  Min Su Kim ,  Seung Jae Lee

Inventor： Sung Soo Lee ,  Min Su Kim ,  Seung Jae Lee

IPC: G11C7/10

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3454

Abstract: Disclosed is a page buffer having a wired-OR type structure and a cache function which is adapted for use in a nonvolatile semiconductor memory device and a method of programming same. The page buffer embeds the cache latch block in relation to the cache function. Moreover, the nonvolatile semiconductor memory device includes an output driver enabling an internal output line to be unidirectional driven, thereby enabling a program-verifying operation using the wired-OR scheme.

Abstract translation: 公开了一种适用于非易失性半导体存储器件的线或OR型结构和高速缓存功能的页缓冲器及其编程方法。 页面缓冲区相对于缓存功能嵌入高速缓存锁存块。 此外，非易失性半导体存储器件包括能够使内部输出线单向驱动的输出驱动器，从而能够进行使用有线方案的程序验证操作。

公开(公告)号：US20080079456A1

公开(公告)日：2008-04-03

申请号：US11778160

申请日：2007-07-16

Applicant: Sung-soo LEE

Inventor： Sung-soo LEE

IPC: G01R31/26

CPC classification number: G01R31/2893 ,  G01R31/2862 ,  G01R31/2865

Abstract: Provided is a test handler for testing a semiconductor device mounted in a test tray with a test head disposed separately below the test tray under predetermined testing condition at high or low temperature. The test handler includes a thermal isolator to maintain constant the predetermined testing condition at high or low temperature when the test chamber and the test head are separated. The thermal isolator is a shutter that is installed below the test chamber to seal or open the test chamber.

Abstract translation: 提供了一种用于测试安装在测试托盘中的半导体器件的测试处理器，其中测试头在高温或低温下的预定测试条件下分开设置在测试托盘下方。 测试处理器包括热隔离器，以在测试室和测试头分离时在高或低温下保持恒定的预定测试条件。 热隔离器是安装在测试室下面以将密封或打开测试室的快门。