公开(公告)号：US11624777B2

公开(公告)日：2023-04-11

申请号：US16857144

申请日：2020-04-23

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Pratik Ghanshambhai Satasia ,  Yew Keong Chong ,  Andy Wangkun Chen ,  Mouli Rajaram Chollangi

IPC: G06F30/3312 ,  G01R31/28 ,  G06F119/12

Abstract: Various implementations described herein are related to a method for constructing integrated circuitry and identifying input signal paths, internal signal paths and output signal paths associated with the integrated circuitry. The method may include generating a timing table for slew-load characterization of the input signal paths, the internal signal paths and the output signal paths. The method may include simulating corner points for the timing table, building diagonal points for the timing table based on the simulated corner points, and building remaining points for the timing table based on the simulated corner points and the diagonal points.

公开(公告)号：US11567741B2

公开(公告)日：2023-01-31

申请号：US16899502

申请日：2020-06-11

Applicant: Arm Limited

Inventor： Mouli Rajaram Chollangi ,  Sriram Thyagarajan ,  Hongwei Zhu ,  Yew Keong Chong ,  Pratik Ghanshambhai Satasia

IPC: G06F8/30 ,  G06F8/38 ,  G06F8/71 ,  G06F16/901 ,  G11C7/00 ,  G06F12/00 ,  G06F8/41

Abstract: Various implementations described herein are directed to a system and methods for memory compiling. For instance, a method may include selecting source corners from a memory compiler configuration and generating a standardized set of memory instances for the selected source corners. Also, the method may include deriving a reduced set of memory instances based on the standardized set of memory instances and building a memory compiler database for a compiler space based on the standardized set of memory instances and the reduced set of memory instances.

公开(公告)号：US20220319586A1

公开(公告)日：2022-10-06

申请号：US17223950

申请日：2021-04-06

Applicant: Arm Limited

Inventor： Rajiv Kumar Sisodia ,  Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Ayush Kulshrestha ,  Munish Kumar

IPC: G11C11/418 ,  G11C11/412 ,  G11C11/419

Abstract: Various implementations described herein are related to a method for accessing a bitcell in an array of bitcells with a wordline and a bitline. The method may perform a precharge operation on the bitline that precharges the bitline after a read cycle and before a write cycle. Also, the method may extend precharge time of the precharge operation between the read cycle and the write cycle, e.g., by modulating a wordline signal on the wordline with early cut-off of the wordline signal on the wordline during the read cycle.

公开(公告)号：US20220309225A1

公开(公告)日：2022-09-29

申请号：US17209903

申请日：2021-03-23

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Yew Keong Chong ,  Sony ,  Andy Wangkun Chen

IPC: G06F30/3953

Abstract: Various implementations described herein are directed to a method for identifying pre-routed metal lines in a higher layer of a multi-layered structure. The method may recognize gaps in the pre-routed metal lines of the higher layer, and also, the method may automatically fill the gaps with conductive stubs to modify the pre-routed metal lines in the higher layer as a continuous metal line with an extended length.

公开(公告)号：US11322197B1

公开(公告)日：2022-05-03

申请号：US17076540

申请日：2020-10-21

Applicant: Arm Limited

Inventor： Rajiv Kumar Sisodia ,  Andy Wangkun Chen ,  Ayush Kulshrestha ,  Sony ,  Sriram Thyagarajan ,  Yew Keong Chong

IPC: G11C5/14 ,  G11C11/418

Abstract: Various implementations described herein are related to a device having wordline drivers coupled to a core array. The device may have backside power network with buried power rails. The device may have header logic coupled to power supply connections of the wordline drivers by way of the buried power rails, and the header logic may be used to power-gate the wordline drivers.

公开(公告)号：US20220077134A1

公开(公告)日：2022-03-10

申请号：US17017551

申请日：2020-09-10

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony

IPC: H01L27/02 ,  H01L27/092 ,  H01L23/48 ,  G06F30/392 ,  G06F30/3953

Abstract: Various implementations described herein refer to a device having logic circuitry with transistors and gate lines. The device may include a backside power network having buried supply rails with at least one buried supply rail having a continuity break. The transistors may be arranged in a cell architecture having an N-well break with the gate lines passing through the N-well break and the continuity break.

公开(公告)号：US20220068813A1

公开(公告)日：2022-03-03

申请号：US17006695

申请日：2020-08-28

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony ,  Ettore Amirante ,  Ayush Kulshrestha

IPC: H01L23/528 ,  H01L27/06 ,  H03K19/0185

Abstract: Various implementations described herein are related to various devices having a frontside power network with frontside supply rails and a backside power network with backside supply rails. The device may include intermixing architecture with transition vias that couple the frontside power network to the backside power network. The intermixing architecture may transition the frontside supply rails of the frontside power network to the backside supply rails of the backside power network.

公开(公告)号：US20220068346A1

公开(公告)日：2022-03-03

申请号：US17006689

申请日：2020-08-28

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony ,  Ettore Amirante ,  Ayush Kulshrestha

IPC: G11C11/4074 ,  G11C11/4094 ,  G11C11/4091 ,  G11C5/14 ,  G11C7/10

Abstract: Various implementations described herein are related to a device having memory circuitry with a bitcell array. The device may include a frontside power network that is coupled to the bitcell array, and the device may include a backside power network that provides power to the bitcell array. The device may include transition vias that couple the backside power network to the frontside power network, and the backside power network may provide power to the bitcell array by way of the transition vias being coupled to the frontside power network.

公开(公告)号：US11145651B2

公开(公告)日：2021-10-12

申请号：US16882634

申请日：2020-05-25

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Kumaraswamy Ramanathan ,  Damayanti Datta

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  G11C11/40 ,  H03K3/012

Abstract: Briefly, embodiments of claimed subject matter relate to devices and methods for modifying, such as decreasing rise time and/or fall time, of a driver signal output. To achieve such modifications in driver output signals, additional gates may be positioned at PMOS and/or NMOS regions of a semiconductor film. In addition, at least in particular embodiments, etching of portions of one or more semiconductor regions may increase compressive or tensile stress, which may further operate to modify driver output signals.

公开(公告)号：US11087834B2

公开(公告)日：2021-08-10

申请号：US16555899

申请日：2019-08-29

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Andy Wangkun Chen ,  Pratik Ghanshambhai Satasia

IPC: G11C11/00 ,  G11C11/419 ,  H03K5/24 ,  G11C11/418

Abstract: Various implementations described herein are directed to a device having various circuitry for reading first data from a memory location in single-port memory and writing second data to the memory location in the single-port memory after reading the first data from the memory location. In some implementations, reading the first data and writing the second data to the memory location are performed in a single operation.