公开(公告)号：US20060280143A1

公开(公告)日：2006-12-14

申请号：US11466270

申请日：2006-08-22

申请人： Anand Dabak ,  Mohammed Nafie ,  Timothy Schmidl ,  Alan Gatherer

发明人： Anand Dabak ,  Mohammed Nafie ,  Timothy Schmidl ,  Alan Gatherer

IPC分类号： H04Q7/00 ,  H04L12/56

CPC分类号： H01Q3/22 ,  H01Q1/2291 ,  H04B1/713 ,  H04B7/0615 ,  H04B7/0697 ,  H04B7/0848 ,  H04W84/18

摘要： A communication circuit (28) is designed with a signal processing circuit (370) arranged to produce a first plurality of data signals and receive a second plurality of data signals. A transmit circuit (364) is coupled to receive the first plurality of data signals and transmit each data signal of the first plurality of data signals on a respective transmit frequency in a predetermined sequence of transmit frequencies. A receive circuit (362) is coupled to receive each data signal of the second plurality of data signals from a remote transmitter on the respective transmit frequency in the predetermined sequence. The receive circuit applies the second plurality of data signals to the signal processing circuit.

摘要翻译： 通信电路（28）被设计成具有被配置为产生第一多个数据信号并接收第二多个数据信号的信号处理电路（370）。 发射电路（364）被耦合以接收第一多个数据信号，并且以预定的发射频率的顺序在相应的发射频率上发射第一多个数据信号的每个数据信号。 接收电路（362）被耦合以便以预定顺序在相应发射频率上从远程发射机接收第二多个数据信号的每个数据信号。 接收电路将第二多个数据信号施加到信号处理电路。

公开(公告)号：US20060252447A1

公开(公告)日：2006-11-09

申请号：US11381414

申请日：2006-05-03

申请人： Tarik Muharemovic ,  Sriram Sundararajan ,  Vijay Sundararajan ,  Alan Gatherer

发明人： Tarik Muharemovic ,  Sriram Sundararajan ,  Vijay Sundararajan ,  Alan Gatherer

IPC分类号： H04B7/00 ,  H04Q7/20

CPC分类号： H04W52/247 ,  H04W52/12 ,  H04W52/221 ,  H04W52/241 ,  H04W52/248

摘要： In this invention the base station utilizes a history of previous TPC commands to provide more deterministic channel behavior. This enables better generation of future TPC commands, SIR estimates and channel estimates. Prior solutions don't utilize previous TPC decisions. This invention provides enhances SIR estimation, channel estimation and power control.

摘要翻译： 在本发明中，基站利用先前TPC命令的历史来提供更确定的信道行为。 这样可以更好地生成未来的TPC命令，SIR估计和信道估计。 先前的解决方案不能利用先前的TPC决策。 本发明提供增强的SIR估计，信道估计和功率控制。

公开(公告)号：US07020827B2

公开(公告)日：2006-03-28

申请号：US10032859

申请日：2001-12-28

申请人： Alan Gatherer ,  Tod D. Wolf

发明人： Alan Gatherer ,  Tod D. Wolf

IPC分类号： H03M13/03 ,  H03M13/00

CPC分类号： H03M13/3905 ,  H03M13/27 ,  H03M13/2957 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/395 ,  H03M13/3972 ,  H03M13/6561

摘要： MAP decoder with cascade architecture. Iterative Turbo decoders can use two such cascade MAP decoders with feedback in conjunction with interleaver and deinterleaver where the MAP decoders generate extrinsic information for iterations. The cascade architecture limits the required number of max* blocks which compute the logarithm of a sum of exponentials as part of the BCJR method.

摘要翻译： MAP解码器具有级联架构。 迭代Turbo解码器可以使用两个这样的级联MAP解码器，其中反馈与交织器和解交织器结合，其中MAP解码器生成用于迭代的外在信息。 级联架构限制了所需数量的max *块，它们计算指数之和的对数作为BCJR方法的一部分。

公开(公告)号：US20060029169A1

公开(公告)日：2006-02-09

申请号：US11246618

申请日：2005-10-07

申请人： Alan Gatherer ,  Tarik Muharemovic ,  Everest Huang ,  Srinath Hosur

发明人： Alan Gatherer ,  Tarik Muharemovic ,  Everest Huang ,  Srinath Hosur

IPC分类号： H04L1/02

CPC分类号： H04L1/06 ,  H04L1/005 ,  H04L1/0066 ,  H04L1/0071 ,  H04L1/0618

摘要： An apparatus and method for transmitting and receiving a bit stream. On the transmission side, coded bits (Y.sub.t) and an interleaved version of the coded bits (X.sub.t) are separately modulated and transmitted. On the reception side, a priori output probabilities produced by a probability generator (34) are combined (112) and then input to a SISO decoder (111). Combined a posteriori output probabilities (115) produced by the SISO decoder are split (113) and then fed back to the probability generator.

摘要翻译： 一种用于发送和接收比特流的装置和方法。 在发送侧，分别调制和发送编码比特（Y.sub.t）和编码比特（X.sub.t）的交织版本。 在接收侧，组合由概率发生器（34）产生的先验输出概率（112），然后输入到SISO解码器（111）。 组合由SISO解码器产生的后验输出概率（115）被分离（113），然后反馈给概率发生器。

公开(公告)号：US06996765B2

公开(公告)日：2006-02-07

申请号：US10259099

申请日：2002-09-27

申请人： Tod D. Wolf ,  Antonio F. Mondragon-Torres ,  Alan Gatherer

发明人： Tod D. Wolf ,  Antonio F. Mondragon-Torres ,  Alan Gatherer

IPC分类号： H03M13/00 ,  H03M13/03 ,  H04L27/06

CPC分类号： H03M13/3905 ,  H03M13/2957 ,  H03M13/3723 ,  H03M13/3972 ,  H03M13/658

摘要： This invention describes implementation approaches for sliding window turbo decoders. Sliding windows are used for both the beta and alpha state metric calculations. Initialization of the beta/alpha prolog sections with data from a previous iteration is employed in conjunction with a reduced length prolog section. For subsequent sliding windows the trellis values of the prolog sections are dynamically initialized based upon data derived from the signal to noise ratio of the calculated extrinsic data or the difference between the two most probable trellis states.

公开(公告)号：US06996118B2

公开(公告)日：2006-02-07

申请号：US09953035

申请日：2001-09-13

申请人： Keith L. Quiring ,  Alan Gatherer

发明人： Keith L. Quiring ,  Alan Gatherer

IPC分类号： H04J3/16

CPC分类号： H04M3/005

摘要： A linecard (175) permits an increased rate connection between a subscriber (15) and a service provider (40) over the PSTN (50) includes an analog interface (152) a digital interface (165) coupled to the digital backplane (170) to the service provider's host server (34), a conversion circuit (258) interspersed between the analog interface (152) and the digital interface (165), and a linecard microcontroller (300) configured to request bandwidth on the backplane (170) A linecard (175) incorporates a codec (250) with a code recognition mechanism (200) to monitor the Pulse Code Modulated (PCM) input from the provider. The code recognition mechanism (200) provides a way to dynamically allocate and deallocate timeslots on the backplane (170).

摘要翻译： 线路卡（175）允许通过PSTN（50）的用户（15）和服务提供商（40）之间的增加的速率连接包括模拟接口（152）耦合到数字背板（170）的数字接口（165） 分布在模拟接口（152）和数字接口（165）之间的转换电路（258）以及被配置为在背板（170）A上请求带宽的线卡微控制器（300）向服务提供商的主机服务器（34） 线卡（175）包含具有代码识别机构（200）的编解码器（250），以监视来自提供商的脉冲编码调制（PCM）输入。 代码识别机制（200）提供了一种在背板（170）上动态地分配和释放时隙的方法。

公开(公告)号：US06996091B2

公开(公告)日：2006-02-07

申请号：US09953036

申请日：2001-09-13

申请人： Keith L. Quiring ,  Alan Gatherer

发明人： Keith L. Quiring ,  Alan Gatherer

IPC分类号： H04L12/66

CPC分类号： H04L12/2865 ,  H04L12/2856 ,  H04L12/2896 ,  H04M3/005 ,  H04M3/007

摘要： A linecard (175) permits an increased rate connection between a subscriber (15) and a service provider (40) over the PSTN (50) includes an analog interface (152) a digital interface (165) coupled to the digital backplane (170) to the service provider's host server (34), a conversion circuit (258) interspersed between the analog interface (152) and the digital interface (165), and a linecard microcontroller (300) configured to request bandwidth on the backplane (170) A linecard (175) incorporates a codec (250) with a code recognition mechanism (200) to monitor the Pulse Code Modulated (PCM) input from the provider. The code recognition mechanism (200) provides a way to dynamically allocate and deallocate timeslots on the backplane (170).

公开(公告)号：US06980605B2

公开(公告)日：2005-12-27

申请号：US09772499

申请日：2001-01-29

申请人： Alan Gatherer ,  Tod D. Wolf ,  Armelle Laine

发明人： Alan Gatherer ,  Tod D. Wolf ,  Armelle Laine

IPC分类号： G06F11/10 ,  H03M13/29 ,  H03M13/39 ,  H03M13/45 ,  H03D1/00 ,  H04L27/06

CPC分类号： H03M13/3905 ,  H03M13/2957 ,  H03M13/3927 ,  H03M13/3972 ,  H03M13/6561

摘要： A turbo decoder in which a sliding-block MAP decoder pipelines the forward-propagating and backward-propagating computations.

摘要翻译： turbo解码器，其中滑块MAP解码器管理正向传播和反向传播的计算。

公开(公告)号：US06930983B2

公开(公告)日：2005-08-16

申请号：US10320205

申请日：2002-12-16

申请人： Stephen J. Perkins ,  Alan Gatherer ,  Krishanasamy Anandakumar ,  Alan V. McCree ,  Vishu Viswanathan

发明人： Stephen J. Perkins ,  Alan Gatherer ,  Krishanasamy Anandakumar ,  Alan V. McCree ,  Vishu Viswanathan

IPC分类号： H04L12/24 ,  H04L12/56 ,  H04L12/66 ,  H04L29/06 ,  H04L29/14 ,  H04L12/26

CPC分类号： H04L41/08 ,  H04L29/06027 ,  H04L41/0206 ,  H04L41/024 ,  H04L41/12 ,  H04L45/00 ,  H04L45/24 ,  H04L45/56 ,  H04L47/2416 ,  H04L65/105 ,  H04L65/4076 ,  H04L65/602 ,  H04L65/605 ,  H04L65/80 ,  H04L67/14 ,  H04L69/40 ,  H04W28/04 ,  H04W40/02 ,  H04W40/20 ,  H04W40/246 ,  H04W84/042 ,  H04W88/08 ,  H04W88/14 ,  H04W88/16

摘要： In one form of the invention, a process of sending real-time information from a sender computer (103) to a receiver computer (105) coupled to the sender computer (103) by a packet network (100) wherein packets (111,113) sometimes become lost, includes steps of directing (441) packets (111) containing the real-time information from the sender computer (103) by at least one path (119) in the packet network (100) to the receiver computer (105), and directing packets (113) containing information dependent on the real-time information from the sender computer (103) by at least one path diversity path (117) in the packet network (100) to the same receiver computer (105).Other forms of the invention encompass other processes, improved packets and packet ensembles (111,113), integrated circuits (610), chipsets (DSP 1721, MCU), computer cards (1651), information storage articles (1511,1611), systems, computers (103,105), gateways (191,193), routers (131,133), cellular telephone handsets (181,189), wireless base stations (183,187), appliances (1721,1731,1741), and packet networks (100), and other forms as disclosed and claimed.

公开(公告)号：US06829290B1

公开(公告)日：2004-12-07

申请号：US09669394

申请日：2000-09-26

申请人： Timothy M. Schmidl ,  Alan Gatherer ,  Srinath Hosur ,  Anand G. Dabak

发明人： Timothy M. Schmidl ,  Alan Gatherer ,  Srinath Hosur ,  Anand G. Dabak

IPC分类号： H04B169

CPC分类号： H04B1/7115 ,  H04B1/709 ,  H04B1/7117 ,  H04B2201/70707

摘要： A wireless receiver (UST). The receiver comprises at least one antenna (ATU) for receiving a plurality of frames (FR) in a form of a plurality of paths. Each of the plurality of frames comprises a plurality of time slots (SLN), and each of the plurality of time slots comprises a plurality of symbols. Further, each of the plurality of paths has a corresponding sample position, wherein the plurality of symbols comprise a primary synchronization code symbol (PSC). The receiver further comprises circuitry (52) for correlating a primary synchronization code across a group of the plurality of symbols, and circuitry for identifying a plurality of path positions within the group. Each of the plurality of path positions corresponds to a respective one of a plurality of largest-amplitude paths represented within the group as detected in response to the circuitry for correlating. Finally, the receiver comprises circuitry for combining (54, 58) the plurality of largest-amplitude paths in response to identification of those paths by the circuitry for identifying.

摘要翻译： 无线接收器（UST）。 接收机包括用于接收多个路径形式的多个帧（FR）的至少一个天线（ATU）。 多个帧中的每一个包括多个时隙（SLN），并且多个时隙中的每一个包括多个符号。 此外，多个路径中的每一个具有对应的采样位置，其中多个符号包括主同步码符号（PSC）。 接收机还包括用于将多个符号组中的主同步码相互关联的电路（52）以及用于识别组内的多个路径位置的电路​​。 多个路径位置中的每一个对应于响应于用于相关的电路检测到的在组内表示的多个最大幅度路径中的相应一个路径位置。 最后，接收机包括用于响应于用于识别的电路的那些路径的识别来组合（54,58）多个最大幅度路径的电路。