公开(公告)号：US10140227B1

公开(公告)日：2018-11-27

申请号：US15087781

申请日：2016-03-31

Applicant: Amazon Technologies, Inc.

Inventor： Georgy Machulsky ,  Nafea Bshara ,  Netanel Israel Belgazal ,  Said Bshara ,  Evgeny Schmeilin

IPC: G06F13/28 ,  G06F13/42

Abstract: A first write transaction is received by a device that includes a transaction identifier and a memory location identifier. The memory location identifies a register or a memory location of a device. A value from the register or memory location is read. A second write transaction is sent to a block of host memory. The second write transaction includes the value and the transaction identifier.

公开(公告)号：US20180278540A1

公开(公告)日：2018-09-27

申请号：US15990300

申请日：2018-05-25

Applicant: Amazon Technologies, Inc.

Inventor： Leah Shalev ,  Brian William Barrett ,  Nafea Bshara ,  Georgy Machulsky

IPC: H04L12/863 ,  H04L12/835 ,  H04L12/861 ,  H04L12/823 ,  H04L29/06 ,  H04L29/08 ,  H04L12/801 ,  G06F15/173 ,  H04L12/707 ,  H04L12/741 ,  H04L1/18

Abstract: Provided are systems and methods for reliable, out-of-order receipt of packets. In some implementations, provided is an apparatus configured to communicate with a network and a host device. The apparatus may receive packets over the network at a receive queue. The packets may originate from a source on the network, and may be received out of order. The apparatus may further, for each received packet, identify a transport context associated with the source and a destination of the packet, and determine whether the packet can be accepted. Upon determining that the packet can be accepted, the apparatus may further identify the one receive queue at which the packet was received; determine a user application to receive the packet, transfer the packet from the one receive queue to a buffer in host memory, and identify an order in which the packet was received with respect to other packets.

公开(公告)号：US20180278539A1

公开(公告)日：2018-09-27

申请号：US15990062

申请日：2018-05-25

Applicant: Amazon Technologies, Inc.

Inventor： Leah Shalev ,  Brian William Barrett ,  Nafea Bshara ,  Georgy Machulsky

IPC: H04L12/863 ,  H04L12/707 ,  H04L12/741 ,  H04L1/18 ,  H04L29/06 ,  H04L12/801 ,  G06F15/173 ,  H04L29/08 ,  H04L12/861

CPC classification number: H04L47/624 ,  G06F15/17331 ,  H04L1/1841 ,  H04L45/24 ,  H04L45/74 ,  H04L47/34 ,  H04L49/90 ,  H04L69/22 ,  H04L69/324 ,  H04L69/326

Abstract: Provided are systems and methods for reliable, out-of-order transmission of packets. In some implementations, provided is an apparatus configured to communicate with a network and a host device. The apparatus may receive messages from the host device at a send queue, where each message includes destination information. The apparatus may further determine, using the destination information and an identify of the send queue, a transport context associated with a destination on the network. The apparatus may further, for each message and using the transport context, generate a packet including the message and transmit the packet over the network. The apparatus may further monitor status for each transmitted packet.

公开(公告)号：US09916269B1

公开(公告)日：2018-03-13

申请号：US15099543

申请日：2016-04-14

Applicant: Amazon Technologies, Inc.

Inventor： Georgy Machulsky ,  Nafea Bshara ,  Netanel Israel Belgazal ,  Evgeny Schmeilin ,  Said Bshara

IPC: G06F13/36 ,  G06F13/28 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F13/404 ,  G06F13/4068 ,  G06F13/4282

Abstract: A packet header is received from a host and written to a header queue. A direct memory access (DMA) descriptor is received from the host and written to a packet descriptor queue. The DMA descriptor points to packet data in a host memory. The packet data is fetched from host memory and the packet header and the packet data are provided to a network interface.