公开(公告)号：US20140353672A1

公开(公告)日：2014-12-04

申请号：US14345864

申请日：2013-12-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Seungjin Choi ,  Heecheol Kim ,  Youngsuk Song ,  Seongyeol Yoo

IPC: H01L27/12

CPC classification number: H01L27/1259 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/134363 ,  G02F2001/134372 ,  G02F2001/134381 ,  G02F2201/124 ,  H01L21/31127 ,  H01L21/32133 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/3244

Abstract: An array substrate, a method for fabricating the same and a display device are disclosed. The array substrate comprises a plurality of gate lines and a plurality of data lines which intersect each other to define a plurality of pixel regions, each of the pixel regions comprises a thin film transistor and further comprises: a base substrate; more than one protrusion disposed apart from each other on the base substrate; a first electrode layer comprising at least one first electrode strip disposed in a gap between adjacent protrusions; a second electrode layer comprising at least one second electrode strip disposed on the protrusions.

Abstract translation: 公开了阵列基板，其制造方法和显示装置。 阵列基板包括多个栅极线和彼此相交以限定多个像素区域的多条数据线，每个像素区域包括薄膜晶体管，还包括：基底; 在基底基板上彼此分开布置的多于一个的突起; 第一电极层，包括设置在相邻突起之间的间隙中的至少一个第一电极条; 第二电极层，包括设置在突起上的至少一个第二电极条。

公开(公告)号：US20140084282A1

公开(公告)日：2014-03-27

申请号：US13703551

申请日：2012-10-25

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhanfeng Cao ,  Xiaoyang Tong ,  Qi Yao ,  Seongyeol Yoo

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/06 ,  H01L29/51 ,  H01L29/786 ,  H01L29/78606

Abstract: Embodiments of the present invention provide a thin film transistor, an array substrate and a display device. The thin film transistor comprises a gate layer, a first insulating layer, an active layer, an etch stop layer and a source/drain electrode layer, wherein the active layer is made of a metal oxide material, the first insulating layer, the active layer, the etch stop layer and the source/drain electrode layer are sequentially stacked from bottom to top, the source/drain electrode layer contains an interval separating a source electrode and a drain electrode therein, the etch stop layer is located below the interval, and the etch stop layer has a width greater than that of the interval, and the first insulating layer comprises a laminate of a first sub-insulation layer and a second sub-insulation layer, the second sub-insulation layer is in contact with the active layer and made of an oxygen-rich insulating material.

Abstract translation: 本发明的实施例提供一种薄膜晶体管，阵列基板和显示装置。 薄膜晶体管包括栅极层，第一绝缘层，有源层，蚀刻停止层和源极/漏极电极层，其中有源层由金属氧化物材料制成，第一绝缘层，有源层 ，蚀刻停止层和源极/漏极电极层从底部到顶部依次层叠，源极/漏极层包含在其中分离源极和漏极的间隔，蚀刻停止层位于间隔的下方，并且 所述蚀刻停止层的宽度大于所述间隔的宽度，并且所述第一绝缘层包括第一次级绝缘层和第二次级绝缘层的叠层，所述第二次级绝缘层与所述有源层接触 并由富氧绝缘材料制成。