公开(公告)号：US12278243B2

公开(公告)日：2025-04-15

申请号：US17529969

申请日：2021-11-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chenyang Zhang ,  Fuqiang Li ,  Xue Dong ,  Meili Wang ,  Xuan Liang ,  Fei Wang ,  Mingxing Wang ,  Zhanfeng Cao ,  Yanling Han ,  Xinxin Zhao

IPC: H01L27/12 ,  H01L25/075 ,  H01L33/62

Abstract: A semiconductor apparatus and a method for manufacturing the semiconductor apparatus are provided. The semiconductor apparatus includes: a base substrate; a plurality of chips arranged on the base substrate each including a chip main body and a plurality of terminals arranged thereon; a plurality of fixed connection portions arranged on the base substrate, and adjacent to the plurality of chips; a terminal expansion layer arranged on the base substrate; and a plurality of expansion wires in the terminal expansion layer and configured to electrically connect the chips, wherein an expansion wire configured to electrically connect two chips includes at least a first wire segment and a second wire segment, and the first wire segment is configured to electrically connect a terminal of a chip and a fixed connection portion adjacent to the chip, and the second wire segment is configured to connect two fixed connection portions between the two chips.

公开(公告)号：US12266738B2

公开(公告)日：2025-04-01

申请号：US17407919

申请日：2021-08-20

Applicant: BOE Technology Group Co., Ltd.

Inventor： Haixu Li ,  Mingxing Wang ,  Guangcai Yuan ,  Zhanfeng Cao ,  Ke Wang ,  Feng Qu

IPC: H01L33/38 ,  H01L25/075 ,  H01L27/15 ,  H01L33/62

Abstract: A driving backplane, a display panel and a display apparatus are provided. The driving backplane includes: a base substrate, and a plurality of connection electrode groups and a plurality of correction structures disposed on the base substrate, each of the connection electrode groups includes: a first connection electrode and a second connection electrode the first connection electrode and the second connection electrode are arranged on a same layer; a first gap is formed between the first connection electrode and the second connection electrode, and a first group of opposite edges includes: an edge, close to the first gap, of the first connection electrode; and an edge, close to the first gap, of the second connection electrode; a second group of opposite edges includes: an edge, far away from the first gap, of the first connection electrode; and an edge, far away from the first gap, of the second connection electrode.

公开(公告)号：US12183748B2

公开(公告)日：2024-12-31

申请号：US18518526

申请日：2023-11-23

Applicant: BOE Technology Group Co., Ltd.

Inventor： Ke Wang ,  Muxin Di ,  Zhiwei Liang ,  Guoqiang Wang ,  Renquan Gu ,  Xiaoxin Song ,  Xiaoyan Zhu ,  Yingwei Liu ,  Zhanfeng Cao

IPC: H01L27/12

Abstract: An array substrate including a display area having a plurality of subpixels is provided. The plurality of subpixels includes a plurality of first subpixels in a display-bonding sub-area and a plurality of second subpixels in a regular display sub-area. The array substrate includes a plurality of thin film transistors on a first side of the base substrate and respectively in the plurality of subpixels. A respective one of the plurality of first subpixels includes a bonding pad on a second side of a base substrate; a lead line electrically connecting a respective one of a plurality of thin film transistors to the bonding pad; and a via extending through the base substrate. The lead line is unexposed in the array substrate. The lead line extends from the first side to the second side of the base substrate through the via, to connect to the bonding pad.

公开(公告)号：US11637166B2

公开(公告)日：2023-04-25

申请号：US16651551

申请日：2019-11-13

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yingwei Liu ,  Qi Yao ,  Ke Wang ,  Zhanfeng Cao ,  Zhiwei Liang ,  Muxin Di ,  Guangcai Yuan ,  Xue Jiang ,  Dongni Liu

IPC: H01L27/32 ,  H01L51/56 ,  H01L51/00

Abstract: The present disclosure relates to a method of manufacturing an array substrate. The method of manufacturing an array substrate may include forming a main via hole in a substrate, filling a first conductive material in the main via hole, and forming a pixel circuit layer on a first surface of the substrate. The pixel circuit layer may include a first via hole. An orthographic projection of the first via hole on the substrate may at least partially overlap the corresponding main via hole.

公开(公告)号：US11581461B2

公开(公告)日：2023-02-14

申请号：US16917921

申请日：2020-07-01

Applicant: BOE Technology Group Co., Ltd.

Inventor： Zhiwei Liang ,  Wenqian Luo ,  Yingwei Liu ,  Zhanfeng Cao ,  Ke Wang

IPC: H01L33/62 ,  H01L27/15 ,  H01L33/00 ,  H01L33/56

Abstract: A display substrate includes a drive substrate and a welding pad provided on the drive substrate and electrically connected with the drive substrate. The display substrate further includes an insulating construction layer provided on the welding pad. The insulating construction layer is provided with a groove for exposing the welding pad. A bonding material is accommodated in the groove, and a micro light emitting diode is electrically connected with the welding pad through the bonding material.

公开(公告)号：US11495623B2

公开(公告)日：2022-11-08

申请号：US16772272

申请日：2019-12-19

Applicant: BOE Technology Group Co., Ltd.

Inventor： Yanan Niu ,  Kuanjun Peng ,  Jiushi Wang ,  Zhanfeng Cao ,  Feng Zhang ,  Qi Yao ,  Wusheng Li ,  Feng Guan ,  Lei Chen ,  Jintao Peng ,  Tingting Zhou

IPC: H01L27/12

Abstract: The present disclosure provides a display substrate and a manufacturing method thereof, and a display device. In the display substrate of the present disclosure, a first transistor comprises a first gate electrode, a first electrode, a second electrode, and a first active layer; and a second transistor comprises a second gate electrode, a third electrode, a fourth electrode, and a second active layers, wherein the first active layer comprises a silicon material, the second active layer comprises an oxide semiconductor material, and wherein the third electrode and the first gate electrode are disposed in the same layer, and the fourth electrode and the first electrode, the second electrodes are disposed in the same layer.

公开(公告)号：US11469261B2

公开(公告)日：2022-10-11

申请号：US16769725

申请日：2019-08-20

Applicant: BOE Technology Group Co., Ltd.

Inventor： Shengguang Ban ,  Zhanfeng Cao ,  Ke Wang ,  Qingzhao Liu ,  Shuilang Dong

IPC: H01L27/14 ,  H01L27/144 ,  G02F1/1362 ,  H01L27/32 ,  G02F1/1368

Abstract: An array substrate is provided. The array substrate includes a display area having a first array of subpixels; and a partially transparent area having a second array of subpixels. The partially transparent area includes a plurality of light emitting regions spaced apart from each other by a substantially transparent non-light emitting region. The second array of subpixels is limited in the plurality of light emitting regions. The array substrate further includes a plurality of photosensors and a plurality of first thin film transistors in the substantially transparent non-light emitting region. A respective one of the plurality of photosensors includes a first polarity semiconductor layer, a second polarity semiconductor layer, and an intrinsic semiconductor layer connecting the first polarity semiconductor layer and the second polarity semiconductor layer.

公开(公告)号：US11256891B2

公开(公告)日：2022-02-22

申请号：US16607192

申请日：2019-05-08

Applicant: BOE Technology Group Co., Ltd.

Inventor： Haixu Li ,  Zhanfeng Cao ,  Jianguo Wang

IPC: G06K9/00 ,  H01L27/32 ,  G02F1/1368

Abstract: An array substrate, a method of manufacturing the array substrate, and a display apparatus are disclosed. The array substrate includes: a base substrate; a plurality of sensing elements disposed on a first side of the base substrate and each configured to convert at least one of a light signal and an acoustic wave signal into an electrical signal; and a plurality of switching devices disposed on a second side of the base substrate opposite to the first side. The plurality of switching devices include a plurality of first switching elements, and each of the plurality of first switching elements is electrically connected to a corresponding one of the plurality of sensing elements to transmit the electrical signal.

公开(公告)号：US11245037B2

公开(公告)日：2022-02-08

申请号：US16616965

申请日：2018-06-19

Applicant: BOE Technology Group Co., Ltd.

Inventor： Shengguang Ban ,  Zhanfeng Cao ,  Qi Yao

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L27/12

Abstract: The present application provides an array substrate. The array substrate includes a base substrate; a light shielding layer on the base substrate; a metal oxide layer on a side of the light shielding layer distal to the base substrate; and an active layer on a side of the metal oxide layer distal to the base substrate. The metal oxide layer includes a metal oxide material. The light shielding layer includes amorphous silicon. An orthographic projection of the light shielding layer on the base substrate substantially overlaps with an orthographic projection of the active layer on the base substrate, and substantially overlaps with an orthographic projection of the metal oxide layer on the base substrate.

公开(公告)号：US20210408088A1

公开(公告)日：2021-12-30

申请号：US16769725

申请日：2019-08-20

Applicant: BOE Technology Group Co., Ltd.

Inventor： Shengguang Ban ,  Zhanfeng Cao ,  Ke Wang ,  Qingzhao Liu ,  Shuilang Dong

IPC: H01L27/144 ,  H01L27/32 ,  G02F1/1362

Abstract: An array substrate is provided. The array substrate includes a display area having a first array of subpixels; and a partially transparent area having a second array of subpixels. The partially transparent area includes a plurality of light emitting regions spaced apart from each other by a substantially transparent non-light emitting region. The second array of subpixels is limited in the plurality of light emitting regions. The array substrate further includes a plurality of photosensors and a plurality of first thin film transistors in the substantially transparent non-light emitting region. A respective one of the plurality of photosensors includes a first polarity semiconductor layer, a second polarity semiconductor layer, and an intrinsic semiconductor layer connecting the first polarity semiconductor layer and the second polarity semiconductor layer.