公开(公告)号：US06358796B1

公开(公告)日：2002-03-19

申请号：US09292360

申请日：1999-04-15

申请人： Yai-Fen Lin ,  Chang-Song Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Juang-Ke Yeh

发明人： Yai-Fen Lin ,  Chang-Song Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Juang-Ke Yeh

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

摘要： A method is provided for forming a split-gate flash memory cell having a shallow trench isolation without the intrusion of a “smiling” gap near the edge of the trench encompassing the first polysilicon layer. This is accomplished by forming two conformal layers lining the interior walls of the trench. An exceptionally thin nitride layer overlying the first conformal oxide layer provides the necessary protection during the oxidation of the first polysilicon layer so as to prevent the “smiling” effect normally encountered in fabricating ultra large scale integrated circuits.

公开(公告)号：US06344997B2

公开(公告)日：2002-02-05

申请号：US09858527

申请日：2001-05-17

申请人： Hung-Cheng Sung ,  Din-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

发明人： Hung-Cheng Sung ,  Din-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

IPC分类号： G11C1604

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  H01L27/115

摘要： In this invention bit lines are ion implanted into a semiconductor substrate in columns beside floating gates of an array of flash memory cells. A control gate overlays each row floating gates and operates as a word lines for the rows of flash memory cells. Each bit line serves a dual purpose of providing a drain for one cell and a source for the adjacent cell. The flash memory cells are programmed, erased and read depending upon the voltages applied to the buried bit lines and the word line structured as a control gate that extends the length of each row. By implanting the bit lines into the semiconductor substrate the flash memory cell can be made smaller improving the density of the flash memory.

公开(公告)号：US06385089B2

公开(公告)日：2002-05-07

申请号：US09851215

申请日：2001-05-08

申请人： Hung-Cheng Sung ,  Din-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

发明人： Hung-Cheng Sung ,  Din-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

IPC分类号： G11C1604

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  H01L27/115

摘要： In this invention bit lines are ion implanted into a semiconductor substrate in columns beside floating gates of an array of flash memory cells. A control gate overlays each row floating gates and operates as a word lines for the rows of flash memory cells. Each bit line serves a dual purpose of providing a drain for one cell and a source for the adjacent cell. The flash memory cells are programmed, erased and read depending upon the voltages applied to the buried bit lines and the word line structured as a control gate that extends the length of each row. By implanting the bit lines into the semiconductor substrate the flash memory cell can be made smaller improving the density of the flash memory.

摘要翻译： 在本发明中，位线被离子注入到闪存单元阵列的浮置栅极旁边的列中的半导体衬底中。 控制栅极叠加每行浮动栅极，并作为闪存单元行的字线工作。 每个位线用于为一个单元提供漏极和用于相邻单元的源的双重目的。 闪存单元被编程，擦除和读取，这取决于施加到掩埋位线的电压和构成为延伸每行的长度的控制栅极的字线。 通过将位线注入到半导体衬底中，可以使闪存单元更小以改善闪存的密度。

公开(公告)号：US06538276B2

公开(公告)日：2003-03-25

申请号：US09755281

申请日：2001-01-08

申请人： Chia-Ta Hsieh ,  Yai-Fen Liu ,  Hung-Cheng Sung ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Liu ,  Hung-Cheng Sung ,  Di-Son Kuo

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

摘要： A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern a gate electrode stack formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Form intermetal dielectric and control gate layers over the substrate covering the stack and the source regions and the drain regions. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Pattern a source line slot in the center of the gate electrode stack down to the substrate. Form source regions through the source line slot. Form drain regions self-aligned with the split gate electrodes and the gate electrode stack.

摘要翻译： 形成分离栅电极MOSFET器件的方法包括以下步骤。 在半导体衬底上形成隧道氧化层。 在隧道氧化物层上形成浮栅电极层。 在浮栅电极层上形成掩蔽帽。 以掩模盖的图案形成由隧道氧化物层和浮栅电极层形成的栅电极堆叠。 在覆盖堆叠和源极区域和漏极区域的衬底上方形成金属间电介质和控制栅极层。 将金属间电介质和控制栅极层图案化成相邻的镜像分离栅电极对。 将栅极电极堆叠的中心的源极线槽图案化为衬底。 通过源线槽形成源区。 形成漏极区域与分离栅电极和栅极电极堆叠自对准。

公开(公告)号：US06245685B1

公开(公告)日：2001-06-12

申请号：US09387441

申请日：1999-09-01

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh

IPC分类号： H01L2100

CPC分类号： H01L27/11521 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/823842 ,  H01L27/115

摘要： A method for forming a square oxide structure or a square floating gate without a rounding effect at its corners. A first dielectric layer is formed on a pad layer for a square oxide structure or a polysilicon layer overlying a gate oxide layer for a floating gate, and a second dielectric layer is formed on the first dielectric layer. The second dielectric layer is patterned to form parallel openings in a first direction using a first photosensitive mask. A second photosensitive mask, having a plurality of parallel openings in a second direction perpendicular to the first direction is formed over the second dielectric layer and the first dielectric layer. The first dielectric layer is etched through square openings where the openings in the second photosensitive mask and the openings in the second dielectric layer intersect, thereby forming square openings in the first dielectric layer. The second photosensitive mask and the second dielectric layer are removed. The square oxide structure is completed by etching a trench in the semiconductor structure and forming an STI or LOCOS. The square floating gate is completed by growing polysilicon oxide structures in the square openings in the first dielectric layer and removing the first dielectric layer to form a pattern of openings therebetween, and etching the polysilicon layer through the pattern of openings between the polysilicon oxide structures forming square floating gate polysilicon regions under the polysilicon oxide hard masks.

摘要翻译： 用于在其角部形成平方氧化物结构或方形浮动栅极而不具有圆化效应的方法。 第一电介质层形成在用于平面氧化物结构的焊盘层或覆盖用于浮置栅极的栅极氧化物层的多晶硅层上，并且第二介电层形成在第一介电层上。 图案化第二电介质层以使用第一感光掩模在第一方向上形成平行的开口。 在第二电介质层和第一电介质层上形成第二光敏掩模，在与第一方向垂直的第二方向上具有多个平行的开口。 通过正方形开口蚀刻第一电介质层，其中第二感光掩模中的开口和第二介电层中的开口相交，从而在第一介电层中形成方形开口。 去除第二光敏掩模和第二介电层。 通过蚀刻半导体结构中的沟槽并形成STI或LOCOS来完成平方氧化物结构。 通过在第一电介质层的正方形开口中生长多晶氧化物结构并去除第一电介质层以形成其间的开口图案来完成正方形浮栅，并且通过形成多晶硅氧化物结构之间的开口图案蚀刻多晶硅层 方形浮栅多晶硅区域下的多晶硅氧化物硬掩模。

公开(公告)号：US06479859B2

公开(公告)日：2002-11-12

申请号：US09777303

申请日：2001-02-06

申请人： Chia-Ta Hsieh ,  Tai-Fen Lin ,  Wen-Ting Chu ,  Chuang-Ke Yeh ,  Hung-Cheng Sung ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Tai-Fen Lin ,  Wen-Ting Chu ,  Chuang-Ke Yeh ,  Hung-Cheng Sung ,  Di-Son Kuo

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to isolation, to source and to word line. This multi-self-aligned structure, which provides the maximum shrinkage of the cell that is possible, is also disclosed. The multi-self-alignment is accomplished by first defining the floating gate at the same time the trench isolation is formed, and then self-aligning the source to the floating gate by using a nitride layer as a hard mask in place of the traditional polyoxide, and finally forming a polysilicon spacer to align the word line to the floating gate. Furthermore, a thin floating gate is used to form a thin and sharp poly tip through the use of a “smiling effect” to advantage. The tip substantially decreases the coupling ratio of the floating gate to the word line for fast erasing speed, while at the same time increasing the coupling of the source to the floating gate with the attendant increase in the programming speed of the split gate flash memory cell.

摘要翻译： 公开了一种用于形成分离栅闪存单元的方法，其中单元的浮置栅极自对准到隔离，源极和字线。 还公开了提供可能的电池的最大收缩率的多自对准结构。 通过首先在形成沟槽隔离的同时首先定义浮栅，然后通过使用氮化物层作为硬掩模来代替传统的多晶氧体来将源自对准到浮栅来实现多自对准 ，并最终形成多晶硅间隔物以将字线对准浮动栅极。 此外，通过使用“微笑效果”，薄的浮动门用于形成薄而尖的多头尖端。 尖端大大降低了浮动栅极与字线的耦合比，以实现快速擦除速度，同时增加了源极与浮栅的耦合，伴随着分流栅闪存单元的编程速度的增加 。

公开(公告)号：US06559501B2

公开(公告)日：2003-05-06

申请号：US09850639

申请日：2001-05-07

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is disclosed for forming a split-gate flash memory cell having a salicidated control gate and self-aligned contacts. Salicidation is normally performed with single gate devices, such as logic devices. In a split-gate where the control gate overlays the floating gate with an intervening intergate oxide layer, it is conventionally incompatible to form self-aligned silicides over the control gate due to its position at a different level from that of the floating gate. Furthermore, oxide spacers that are normally used are inadequate when applied to memory cells. It is shown in the present invention that by a judicious use of an additional nitride/oxide layer over the control gate, oxide spacers can now be used effectively to delineate areas on the control gate that can be silicided and also self-aligned. Hence, with this method, salicidation and self-aligned contact techniques can be used not only on the same VLSI and ULSI chips having both peripheral logic devices and memory devices, but also in memory devices themselves.

摘要翻译： 公开了一种用于形成具有盐化控制栅极和自对准触点的分离栅极闪存单元的方法。 通常用单栅极器件（例如逻辑器件）执行致敏。 在分支栅极中，其中控制栅极与中间栅极氧化物层覆盖浮置栅极，因为它们的位置与浮置栅极的位置处于不同的水平位置，因此在控制栅极上形成自对准硅化物是常规的不相容的。 此外，通常使用的氧化物间隔物在应用于存储单元时是不充分的。 在本发明中显示，通过在控制栅极上明智地使用另外的氮化物/氧化物层，现在可以有效地使用氧化物间隔物来描绘控制栅上可被硅化并且自对准的区域。 因此，利用这种方法，不仅可以使用具有外围逻辑器件和存储器件的同一VLSI和ULSI芯片，而且可以用于存储器件本身中，可以使用水化和自对准接触技术。

公开(公告)号：US06284596B1

公开(公告)日：2001-09-04

申请号：US09213453

申请日：1998-12-17

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is disclosed for forming a split-gate flash memory cell having a salicidated control gate and self-aligned contacts. Salicidation is normally performed with single gate devices, such as logic devices. In a split-gate where the control gate overlays the floating gate with an intervening intergate oxide layer, it is conventionally incompatible to form self-aligned silicides over the control gate due to its position at a different level from that of the floating gate. Furthermore, oxide spacers that are normally used are inadequate when applied to memory cells. It is shown in the present invention that by a judicious use of an additional nitride/oxide layer over the control gate, oxide spacers can now be used effectively to delineate areas on the control gate that can be silicided and also self-aligned. Hence, with this method, salicidation and self-aligned contact techniques can be used not only on the same VLSI and ULSI chips having both peripheral logic devices and memory devices, but also in memory devices themselves.

摘要翻译： 公开了一种用于形成具有盐化控制栅极和自对准触点的分离栅极闪存单元的方法。 通常用单栅极器件（例如逻辑器件）执行致敏。 在分支栅极中，其中控制栅极与中间栅极氧化物层覆盖浮置栅极，因为它们的位置与浮置栅极的位置处于不同的水平位置，因此在控制栅极上形成自对准硅化物是常规的不相容的。 此外，通常使用的氧化物间隔物在应用于存储单元时是不充分的。 在本发明中显示，通过在控制栅极上明智地使用另外的氮化物/氧化物层，现在可以有效地使用氧化物间隔物来描绘控制栅上可被硅化并且自对准的区域。 因此，利用这种方法，不仅可以使用具有外围逻辑器件和存储器件的同一VLSI和ULSI芯片，而且可以用于存储器件本身中，可以使用水化和自对准接触技术。

公开(公告)号：US06204126B1

公开(公告)日：2001-03-20

申请号：US09506930

申请日：2000-02-18

申请人： Chia-Ta Hsieh ,  Tai-Fen Lin ,  Wen-Ting Chu ,  Chuang-Ke Yeh ,  Hung-Cheng Sung ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Tai-Fen Lin ,  Wen-Ting Chu ,  Chuang-Ke Yeh ,  Hung-Cheng Sung ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to isolation, to source and to word line. This multi-self-aligned structure, which provides the maximum shrinkage of the cell that is possible, is also disclosed. The multi-self-alignment is accomplished by first defining the floating gate at the same time the trench isolation is formed, and then self-aligning the source to the floating gate by using a nitride layer as a hard mask in place of the traditional polyoxide, and finally forming a polysilicon spacer to align the word line to the floating gate. Furthermore, a thin floating gate is used to form a thin and sharp poly tip through the use of a “smiling effect” to advantage. The tip substantially decreases the coupling ratio of the floating gate to the word line for fast erasing speed, while at the same time increasing the coupling of the source to the floating gate with the attendant increase in the programming speed of the split gate flash memory cell.

摘要翻译： 公开了一种用于形成分离栅闪存单元的方法，其中单元的浮置栅极自对准到隔离，源极和字线。 还公开了提供可能的电池的最大收缩率的多自对准结构。 通过首先在形成沟槽隔离的同时首先定义浮栅，然后通过使用氮化物层作为硬掩模来代替传统的多晶氧体来将源自对准到浮栅来实现多自对准 ，并最终形成多晶硅间隔物以将字线对准浮动栅极。 此外，通过使用“微笑效果”，薄的浮动门用于形成薄而尖的多头尖端。 尖端大大降低了浮动栅极与字线的耦合比，以实现快速擦除速度，同时增加了源极与浮栅的耦合，伴随着分流栅闪存单元的编程速度的增加 。

公开(公告)号：US06403494B1

公开(公告)日：2002-06-11

申请号：US09638300

申请日：2000-08-14

申请人： Wen-Ting Chu ,  Di-Son Kuo ,  Jack Yeh ,  Chia-Ta Hsieh ,  Chuan-Li Chang

发明人： Wen-Ting Chu ,  Di-Son Kuo ,  Jack Yeh ,  Chia-Ta Hsieh ,  Chuan-Li Chang

IPC分类号： H01L2100

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to a shallow trench isolation (STI), which in turn makes it self-aligned to source and to word line. This will advantageously affect a shrinkage in the size of the memory cell. In a first embodiment, the close self-alignment is made possible through a new use of an anti-reflective coating (ARC) in the various process steps of the making of the cell. In the second embodiment, a low-viscosity material is used in such a manner so as to enable self-alignment of the floating gate to the STI in a simple way.

摘要翻译： 公开了一种用于形成分裂栅极闪存单元的方法，其中单元的浮置栅极自对准到浅沟槽隔离（STI），其又使得其自对准到源极和字线。 这将有利地影响存储器单元的尺寸的收缩。 在第一实施例中，通过在制造电池的各种工艺步骤中新的使用抗反射涂层（ARC）使得紧密的自对准成为可能。 在第二实施例中，以这样的方式使用低粘度材料，以便能够以简单的方式使浮动栅极与STI的自对准。