公开(公告)号：US07653795B2

公开(公告)日：2010-01-26

申请号：US12068598

申请日：2008-02-08

申请人： David Michael Bull

发明人： David Michael Bull

IPC分类号： G06F9/312 ,  G06F11/16

CPC分类号： G06F13/1626 ,  G06F9/383 ,  G06F9/3832 ,  G06F9/3836 ,  G06F9/3857 ,  G06F13/1642 ,  G11C7/1039

摘要： A method and integrated circuit for accessing data in a pipelined data processing apparatus in which the operating conditions of the pipelined data processing apparatus are such that metastable signals may occur on at least the boundaries of the pipelined stages is disclosed. The method comprises the steps of: receiving an indication that an instruction is to be processed by the pipelined data processing apparatus; generating a memory access prediction signal, the memory access prediction signal having a value indicative of whether or not the instruction is likely to cause a read access from a memory; generating a predicted memory access control value from the memory access prediction signal, the predicted memory access control value being generated to achieve and maintain a valid logic level for at least a sampling period thereby preventing any metastability in the predicted memory access control value; and in the event that the predicted memory access control value indicates that a read access is likely to occur, causing a read access to be initiated from the memory. Through this approach, an indication that an instruction is to be processed by the pipelined data processing apparatus is received and a memory access prediction signal indicative of whether or not the instruction is likely to cause a read access from a memory is then generated. The predicted memory access control signal is generated in a way which prevents any metastability being present in that signal. Hence, the signals used in a read access are prevented from being metastable which removes the possibility that metastable signals are used directly in the arbitration of data accesses. Also, the metastable signals may be prevented from being propagated from stage to stage.

摘要翻译： 公开了一种用于访问流水线数据处理装置中的数据的方法和集成电路，其中流水线数据处理装置的操作条件使得可在至少流水线级的边界上发生亚稳信号。 该方法包括以下步骤：接收由流水线数据处理装置处理指令的指示; 生成存储器访问预测信号，所述存储器访问预测信号具有指示所述指令是否可能导致来自存储器的读取访问的值; 从所述存储器访问预测信号生成预测存储器访问控制值，生成所述预测存储器访问控制值以实现并维持至少采样周期的有效逻辑电平，从而防止所述预测存储器访问控制值中的任何亚稳态; 并且在预测的存储器访问控制值指示可能发生读取访问的情况下，导致从存储器发起读取访问。 通过这种方法，接收到由流水线数据处理装置处理指令的指示，然后产生指示是否可能引起来自存储器的读取访问的存储器访问预测信号。 预测的存储器访问控制信号以防止该信号中存在任何亚稳态的方式产生。 因此，在读访问中使用的信号被阻止为亚稳态，这消除了在数据访问仲裁中直接使用亚稳态信号的可能性。 此外，可以防止亚稳态信号从一个阶段传播到另一个阶段。

公开(公告)号：US07574314B2

公开(公告)日：2009-08-11

申请号：US11898923

申请日：2007-09-17

申请人： Simon Andrew Ford ,  David Michael Bull ,  Alastair David Reid

发明人： Simon Andrew Ford ,  David Michael Bull ,  Alastair David Reid

IPC分类号： G01R29/02 ,  G01R25/00

CPC分类号： G06F21/755

摘要： A circuit for a data processing apparatus and a method for detecting spurious signals is disclosed, the circuit comprising a data input operable to receive digital signal values, spurious signal detection logic operable to monitor a digital signal value within the circuit, and to determine at least one of: a safe time window during which it is expected that the digital signal values input into the circuit may cause data transitions in the monitored digital signal value and a transition time window in which it is expected a data transition will occur; and in response to detecting either a data transition in the monitored digital signal value outside of the at least one safe time window or no data transition in the transition window, the spurious signal detection logic is operable to output a detection signal.

摘要翻译： 公开了一种用于数据处理装置的电路和用于检测杂散信号的方法，所述电路包括可操作以接收数字信号值的数据输入，可操作以监视电路内的数字信号值的寄生信号检测逻辑，并至少确定 其中之一是安全时间窗口，期望输入到电路中的数字信号值可能导致监视的数字信号值中的数据转换和预期将发生数据转换的转换时间窗口; 并且响应于检测到在所述至少一个安全时间窗口之外的所监视的数字信号值中的数据转换或者在转换窗口中没有数据转换，所述杂散信号检测逻辑可操作以输出检测信号。

公开(公告)号：US20080097713A1

公开(公告)日：2008-04-24

申请号：US11898923

申请日：2007-09-17

申请人： Simon Andrew Ford ,  David Michael Bull ,  Alastair David Reid

发明人： Simon Andrew Ford ,  David Michael Bull ,  Alastair David Reid

IPC分类号： G01R29/00

CPC分类号： G06F21/755

摘要： A circuit for a data processing apparatus is disclosed, said circuit comprising a data input operable to receive digital signal values, said circuit comprising: spurious signal detection logic operable to monitor a digital signal value within said circuit, and determine at least one of: a safe time window during which it is expected that said digital signal values input into said circuit may cause data transitions in said monitored digital signal value and a transition time window in which it is expected a data transition will occur; and in response to detecting either a data transition in said monitored digital signal value outside of said at least one safe time window or no data transition in said transition window, said spurious signal detection logic is operable to output a detection signal.

摘要翻译： 公开了一种用于数据处理装置的电路，所述电路包括可操作以接收数字信号值的数据输入，所述电路包括：伪信号检测逻辑，可操作以监视所述电路内的数字信号值，并确定以下各项中的至少一个： 安全时间窗口，期望输入到所述电路的所述数字信号值可能导致所述监视的数字信号值中的数据转换和预期将发生数据转换的转换时间窗口; 并且响应于检测到在所述至少一个安全时间窗口之外的所述监视的数字信号值中的数据转换或者在所述转换窗口中没有数据转换，所述寄生信号检测逻辑可操作以输出检测信号。

公开(公告)号：US06172530B2

公开(公告)日：2001-01-09

申请号：US09335696

申请日：1999-06-18

申请人： David Michael Bull ,  Andrew Christopher Rose

发明人： David Michael Bull ,  Andrew Christopher Rose

IPC分类号： G11C800

CPC分类号： G11C8/00

摘要： A decoder is provided for generating N output signals, the decoder comprising a precharged gate structure arranged to receive two or more input signals and to generate N intermediate signals. In a precharge phase, the precharged gate structure is arranged to output the N intermediate signals at a first logic value, and in an evaluate phase the precharged gate structure is arranged to maintain a first intermediate signal at the first logic value, and to cause all other intermediate signals to transition to a second logic value. Further, self-timed logic is provided for receiving the N intermediate signals, and for generating the N output signals, the self-timed logic being arranged, during the precharge phase, to generate the N output signals at the second logic value, and during the evaluate phase to cause a first output signal corresponding to the first intermediate signal to transition to the first logic value. The self-timed logic is further arranged to generate each output signal from the corresponding intermediate signal as qualified to predetermined other intermediate signal, such that the transition of the first output signal to the first logic value is delayed by a first predetermined time after the predetermined other intermediate signal has transitioned to the second logic value.

摘要翻译： 提供了用于产生N个输出信号的解码器，该解码器包括预充电栅极结构，其被布置为接收两个或更多个输入信号并产生N个中间信号。 在预充电阶段，预充电栅极结构被布置为以第一逻辑值输出N个中间信号，并且在评估阶段中，预充电栅结构被布置成将第一中间信号保持在第一逻辑值，并且使所有 其他中间信号转换到第二逻辑值。 此外，提供自定时逻辑用于接收N个中间信号，并且为了产生N个输出信号，在预充电阶段期间，自定时逻辑被布置为以第二逻辑值生成N个输出信号，并且在 所述评估阶段使得对应于所述第一中间信号的第一输出信号转变到所述第一逻辑值。 自定时逻辑还被布置为从对应的中间信号产生符合预定的其他中间信号的每个输出信号，使得第一输出信号到第一逻辑值的转变在预定的第一预定时间后延迟第一预定时间 其他中间信号已经转换到第二逻辑值。