公开(公告)号：US09075622B2

公开(公告)日：2015-07-07

申请号：US12010318

申请日：2008-01-23

申请人： Peter Richard Greenhalgh ,  Andrew Christopher Rose

发明人： Peter Richard Greenhalgh ,  Andrew Christopher Rose

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3875 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/30196 ,  G06F9/382 ,  G06F9/3861

摘要： In a data processing system, data representing program instructions is fetched from memory, each instruction being from one of a plurality of sets of instructions including at least first and second sets of instructions and each program instruction within the fetched data comprising one or more blocks to be pre-decoded, each block representing a portion of an instruction. Pre-decoding circuitry is configured to perform pre-decoding operations on the blocks. For at least one portion of an instruction from the first set of instructions and at least one portion of an instruction from the second set of instructions the pre-decoding operation performed on a block fetched from memory is independent of whether the block is identified as representing the at least one portion of an instruction from the first set of instructions or as the at least one portion of an instruction from the second set of instructions.

公开(公告)号：US08954715B2

公开(公告)日：2015-02-10

申请号：US13422539

申请日：2012-03-16

申请人： Vladimir Vasekin ,  Andrew Christopher Rose ,  Allan John Skillman ,  Antony John Penton

发明人： Vladimir Vasekin ,  Andrew Christopher Rose ,  Allan John Skillman ,  Antony John Penton

IPC分类号： G06F9/38 ,  G06F11/267

CPC分类号： G06F9/38 ,  G06F9/3851 ,  G06F11/267

摘要： A multithreading processor 4 interleaves program instructions from different program threads to perform fine grained multithreading. Thread performance monitoring circuitry 30 monitors performance parameters of individual program threads to generate performance values. Issue control circuitry 28 reads these performance values to determine which program thread is next selected to be active when a thread switch event occurs. The performance parameters measured may include the proportion of cycles in which a program thread is able to provide a program instruction for execution by the execution circuitry 12 within the processor 4.

摘要翻译： 多线程处理器4交织来自不同程序线程的程序指令，以执行细粒度多线程。 线程性能监视电路30监视各个程序线程的性能参数以产生性能值。 问题控制电路28读取这些性能值，以确定当线程切换事件发生时下一个选择哪个程序线程处于活动状态。 测量的性能参数可以包括程序线程能够提供用于由处理器4内的执行电路12执行的程序指令的循环的比例。

公开(公告)号：US08756377B2

公开(公告)日：2014-06-17

申请号：US12656538

申请日：2010-02-02

申请人： Simon John Craske ,  Antony John Penton ,  Loic Pierron ,  Andrew Christopher Rose

发明人： Simon John Craske ,  Antony John Penton ,  Loic Pierron ,  Andrew Christopher Rose

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0804 ,  G06F2212/1024 ,  Y02D10/13

摘要： An apparatus for storing data that is being processed is disclosed. The apparatus comprises: a cache associated with a processor and for storing a local copy of data items stored in a memory for use by the processor, monitoring circuitry associated with the cache for monitoring write transaction requests to the memory initiated by a further device, the further device being configured not to store data in the cache. The monitoring circuitry is responsive to detecting a write transaction request to write a data item, a local copy of which is stored in the cache, to block a write acknowledge signal transmitted from the memory to the further device indicating the write has completed and to invalidate the stored local copy in the cache and on completion of the invalidation to send the write acknowledge signal to the further device.

摘要翻译： 公开了一种用于存储正在处理的数据的装置。 该装置包括：与处理器相关联的用于存储在存储器中用于由处理器使用的数据项的本地副本的高速缓存，用于监控与高速缓存相关联的监视电路，用于监视由另一设备发起的存储器的写事务请求， 进一步的设备被配置为不将数据存储在高速缓存中。 监视电路响应于检测到写入事务请求来写入其本地副本存储在高速缓存中的数据项，以阻止从存储器发送到指示写入已完成的另一设备的写入确认信号，并使其无效 存储的本地副本在缓存中并完成无效，以将写入确认信号发送到另一个设备。

公开(公告)号：US08484508B2

公开(公告)日：2013-07-09

申请号：US12656068

申请日：2010-01-14

申请人： Antony John Penton ,  Simon Andrew Ford ,  Andrew Christopher Rose

发明人： Antony John Penton ,  Simon Andrew Ford ,  Andrew Christopher Rose

IPC分类号： G06F11/00

CPC分类号： G06F11/1641

摘要： A data processing apparatus and method provide fault tolerance when executing a sequence of data processing operations. The data processing apparatus has processing circuitry for performing the sequence of data processing operations, and a redundant copy of that processing circuitry for operating in parallel with the processing circuitry, and for performing the same sequence of data processing operations. Error detection circuitry detects an error condition when output data generated by the processing circuitry differs from corresponding output data generated by the redundant copy. Shared prediction circuitry generates predicted data input to both the processing circuitry and the redundant copy, with the processing circuitry and redundant copy then performing speculative processing of one or more data processing operations in dependence on that predicted data. Each of the processing circuitry and the redundant copy include checking circuitry for determining whether the speculative processing was correct, and initiating corrective action if the speculative processing was not correct. By sharing the prediction circuitry rather than replicating it within both the processing circuitry and the redundant copy, significant area and power consumption benefits can be achieved without affecting the ability of the apparatus to detect faults.

摘要翻译： 数据处理装置和方法在执行数据处理操作的序列时提供容错。 数据处理装置具有用于执行数据处理操作序列的处理电路，以及用于与处理电路并联操作并用于执行相同数据处理操作序列的该处理电路的冗余副本。 当由处理电路产生的输出数据与由冗余副本产生的相应输出数据不同时，错误检测电路检测错误状况。 共享预测电路产生输入到处理电路和冗余副本的预测数据，处理电路和冗余副本然后根据该预测数据执行一个或多个数据处理操作的推测处理。 处理电路和冗余副本中的每一个包括用于确定推测性处理是否正确的检查电路，以及如果推测性处理不正确则启动校正动作。 通过共享预测电路而不是在处理电路和冗余副本中进行复制，可以在不影响设备检测故障的能力的情况下实现显着的面积和功耗优点。

公开(公告)号：US20120260070A1

公开(公告)日：2012-10-11

申请号：US13422539

申请日：2012-03-16

申请人： Vladimir VASEKIN ,  Andrew Christopher Rose ,  Allan John Skillman ,  Antony John Penton

发明人： Vladimir VASEKIN ,  Andrew Christopher Rose ,  Allan John Skillman ,  Antony John Penton

IPC分类号： G06F9/30

CPC分类号： G06F9/38 ,  G06F9/3851 ,  G06F11/267

摘要： A multithreading processor 4 interleaves program instructions from different program threads to perform fine grained multithreading. Thread performance monitoring circuitry 30 monitors performance parameters of individual program threads to generate performance values. Issue control circuitry 28 reads these performance values to determine which program thread is next selected to be active when a thread switch event occurs. The performance parameters measured may include the proportion of cycles in which a program thread is able to provide a program instruction for execution by the execution circuitry 12 within the processor 4.

摘要翻译： 多线程处理器4交织来自不同程序线程的程序指令，以执行细粒度多线程。 线程性能监视电路30监视各个程序线程的性能参数以产生性能值。 问题控制电路28读取这些性能值，以确定当线程切换事件发生时下一个选择哪个程序线程处于活动状态。 测量的性能参数可以包括程序线程能够提供用于由处理器4内的执行电路12执行的程序指令的循环的比例。

公开(公告)号：US08190973B2

公开(公告)日：2012-05-29

申请号：US12004511

申请日：2007-12-21

申请人： Antony John Penton ,  Andrew Christopher Rose ,  Paul Stanley Hughes

发明人： Antony John Penton ,  Andrew Christopher Rose ,  Paul Stanley Hughes

IPC分类号： G06F11/00

CPC分类号： G06F11/141 ,  G06F11/1666 ,  G06F11/20 ,  G11C2029/0411

摘要： A data processing apparatus is provided in which a processing unit, by means of a read access request, accesses a storage device which stores data values and error data associated with those data values. When the processing unit accesses a data value in the storage device, error detection circuitry detects if an error is present in that data value and, if necessary, error correction circuitry corrects the read data value. An error cache having at least one entry stores corrected replacement data values, a corrected data value being allocated into an entry of the error cache for every corrected data value that is generated, and the read access request is re-performed. Replacement data values are read from the error cache in preference to data values stored in the storage device. This ensures that the retry mechanism will succeed irrespective of whether the error was a soft error or a hard error. Thus, if any hard errors do occur during normal operation of the storage device, they can effectively be temporarily corrected through use of the error cache to ensure that the retry mechanism proceeds correctly.

摘要翻译： 提供了一种数据处理装置，其中处理单元通过读取访问请求访问存储与这些数据值相关联的数据值和错误数据的存储设备。 当处理单元访问存储设备中的数据值时，错误检测电路检测该数据值中是否存在错误，如果需要，错误检测电路校正读取的数据值。 具有至少一个入口的错误高速缓存存储校正后的替换数据值，将校正后的数据值分配给错误高速缓冲存储器的条目，以生成每个校正数据值，并重新执行读访问请求。 替换数据值优先于存储在存储设备中的数据值从错误缓存读取。 这样可以确保重试机制成功，无论错误是软错误还是硬错误。 因此，如果在存储设备的正常操作期间发生任何硬错误，则可以通过使用错误高速缓存来有效地暂时地修正它们，以确保重试机制正确地进行。

公开(公告)号：US07941584B2

公开(公告)日：2011-05-10

申请号：US12382939

申请日：2009-03-26

申请人： Alex James Waugh ,  Andrew Christopher Rose

发明人： Alex James Waugh ,  Andrew Christopher Rose

IPC分类号： G06F13/00

CPC分类号： G06F13/4022

摘要： A data processing apparatus and method are provided for performing hazard detection in a series of access requests issued by processing circuitry for handling by one or more slaves. The requests include one or more write access requests to be performec by an addressed slave device. Hazard detection circuitry comprises a pending write access history storage having at least one buffer and at least one counter for keeping a record of each pending write access request. Update circuitry responds receipt of a write access request to perform an update process to identify that write access request as a pending write access request in one of the buffers, and if the identity of another pending write access request is overwritten by that update process, to increment a count value a counter. Hazard checking circuitry is then responsive to at least a subset of the access requests to be issued by the processing circuitry, to reference pending write access history storage in order to determine whether a hazard condition occurs. The manner in which the update circuitry jses a combination of buffers aid counters to keep a record of each pending write access request provides improved performance with respect to known prior art techniques, without the hardware cost that would be associated with increasing the number of buffers.

摘要翻译： 提供了一种数据处理装置和方法，用于在由一个或多个从属装置处理的处理电路发出的一系列访问请求中执行危险检测。 请求包括由寻址的从设备执行的一个或多个写访问请求。 危险检测电路包括具有至少一个缓冲器和至少一个用于保持每个未决写入访问请求的记录的计数器的待决写入访问历史存储器。 更新电路响应接收写入访问请求以执行更新处理，以将该写入访问请求识别为缓冲器之一中的待决写入访问请求，并且如果该更新过程覆盖另一待决写入访问请求的标识，则 增加计数值计数器。 危害检查电路然后响应于要由处理电路发出的访问请求的至少一个子集，以参考未决的写入访问历史存储，以便确定是否发生危险状况。 更新电路以缓冲器组合的方式辅助计数器以保持每个未决写入访问请求的记录提供了相对于已知的现有技术的改进的性能，而没有与增加缓冲器数量相关联的硬件成本。

公开(公告)号：US07925866B2

公开(公告)日：2011-04-12

申请号：US12314095

申请日：2008-12-03

申请人： Peter Richard Greenhalgh ,  Andrew Christopher Rose ,  Simon John Craske ,  Max Zardini

发明人： Peter Richard Greenhalgh ,  Andrew Christopher Rose ,  Simon John Craske ,  Max Zardini

IPC分类号： G06F9/30

CPC分类号： G06F9/30185 ,  G06F9/30149 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3842 ,  G06F9/3861

摘要： A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-decoding circuitry receives the instructions fetched from the memory and performs a pre-decoding operation to generate corresponding pre-decoded instructions, with those pre-decoded instructions then being stored in a cache for access by the processing circuitry. The pre-decoding circuitry performs the pre-decoding operation assuming a speculative processor state, and the cache is arranged to store an indication of the speculative processor state in association with the pre-decoded instructions. The processing circuitry is then arranged only to execute an instruction in the sequence using the corresponding pre-decoded instruction from the cache if a current processor state of the processing circuitry matches the indication of the speculative processor state stored in the cache for that instruction. This provides a simple and effective mechanism for detecting instructions that have been corrupted by the pre-decoding operation due to an incorrect assumption of processor state.

摘要翻译： 提供了一种用于处理由处理电路执行的指令的数据处理装置和方法。 处理电路具有多个处理器状态，每个处理器状态具有与其相关联的不同指令集。 预解码电路接收从存储器取出的指令，并执行预解码操作以产生相应的预解码指令，然后将那些预先解码的指令存储在高速缓存中以供处理电路访问。 预解码电路在假设处理器状态下执行预解码操作，并且高速缓存被配置为存储与预解码指令相关联的推测性处理器状态的指示。 如果处理电路的当前处理器状态与存储在该指令的高速缓存中的推测性处理器状态的指示相匹配，则处理电路然后被布置为仅使用来自高速缓存的相应的预解码指令来执行序列中的指令。 这提供了一种用于检测由于处理器状态的不正确假设而被预解码操作损坏的指令的简单而有效的机制。

公开(公告)号：US07900019B2

公开(公告)日：2011-03-01

申请号：US11414547

申请日：2006-05-01

申请人： Vladimir Vasekin ,  Andrew Christopher Rose ,  David Kevin Hart ,  Javed Osmany

发明人： Vladimir Vasekin ,  Andrew Christopher Rose ,  David Kevin Hart ,  Javed Osmany

IPC分类号： G06F13/00

CPC分类号： G06F9/383 ,  G06F9/342 ,  G06F9/3832 ,  G06F12/0215 ,  G06F12/0292 ,  G06F12/06

摘要： A data processing apparatus having a plurality of memories is provided in which address generation logic (109) outputs to at least one of the plurality of memories a target memory address corresponding to the data to be accessed. Target memory prediction logic (113) outputs a prediction indicating in which one of the plurality of memories a target data is stored. The target memory prediction logic (113) outputs the prediction in the same processing cycle as the output of the target memory address by the address generation logic (109). An associated method is also provided.

摘要翻译： 提供具有多个存储器的数据处理装置，其中地址生成逻辑（109）向多个存储器中的至少一个输出与要访问的数据相对应的目标存储器地址。 目标存储器预测逻辑（113）输出指示多个存储器中的哪个存储器存储目标数据的预测。 目标存储器预测逻辑（113）通过地址生成逻辑（109）在与目标存储器地址的输出相同的处理周期中输出预测。 还提供了相关联的方法。

公开(公告)号：US20090313507A1

公开(公告)日：2009-12-17

申请号：US12155926

申请日：2008-06-11

申请人： Andrew Brookfield Swaine ,  Michael John Williams ,  David Kevin Hart ,  Andrew Christopher Rose

发明人： Andrew Brookfield Swaine ,  Michael John Williams ,  David Kevin Hart ,  Andrew Christopher Rose

IPC分类号： G06F11/34

CPC分类号： G06F11/348 ,  G06F11/3636

摘要： A data processing apparatus is provided having a plurality of processing circuits each having access to a memory. Tracing circuitry is provided for generating a stream of trace data for generating a stream of trace data corresponding to at least one of the plurality of processing circuits. Selection circuitry is provided to enable selective switching of the tracing circuitry from generating a first trace data stream corresponding to a first one of the plurality of processing circuits generating a second different trace data stream corresponding to a different one of the plurality of processing circuits. The selective switching is performed in dependence upon processing state information associating with one or more of the plurality of processing circuits. A corresponding method and computer program product are also provided.

摘要翻译： 提供了一种数据处理装置，其具有各自具有访问存储器的多个处理电路。 跟踪电路被提供用于产生跟踪数据流，用于产生对应于多个处理电路中的至少一个的跟踪数据流。 提供选择电路以使得跟踪电路的选择性切换不产生与多个处理电路中的第一个处理电路相对应的第一跟踪数据流，从而生成对应于多个处理电路中的不同处理电路的第二不同跟踪数据流。 根据与多个处理电路中的一个或多个相关联的处理状态信息执行选择性切换。 还提供了相应的方法和计算机程序产品。