公开(公告)号：US09048305B2

公开(公告)日：2015-06-02

申请号：US13998210

申请日：2013-10-15

申请人： Ishiang Shih ,  Chunong Qiu ,  Cindy X. Qiu ,  Yi-Chi Shih

发明人： Ishiang Shih ,  Chunong Qiu ,  Cindy X. Qiu ,  Yi-Chi Shih

IPC分类号： H01L29/66 ,  H01L29/778

CPC分类号： H01L29/7787 ,  H01L29/045 ,  H01L29/2003

摘要： In HEMTs based on III-nitrides epitaxial films or GaAs, AlGaAs and InGaAs epitaxial films, unwanted microcracks are often formed in the composite epitaxial layers in the channel region during fabrication and operation. These microcracks are caused by strain or stresses due to lattice mismatch and thermal expansion coefficient differences between materials and substrate's. Those microcracks will bring about an increase in source to drain resistance and lead to performance and reliability degradation of the HEMTs and the MMICs containing them. The present invention provides HEMTs with minimized effects of the unwanted microcracks by aligning the channel region long axis to a certain direction so that the channel region long axis forms a right angle with axis of at least one type of the microcracks.

摘要翻译： 在基于III族氮化物外延膜或GaAs，AlGaAs和InGaAs外延膜的HEMT中，在制造和操作期间通常在沟道区域中的复合外延层中形成不期望的微裂纹。 这些微裂纹是由于材料和衬底之间的晶格失配和热膨胀系数差异引起的应变或应力引起的。 这些微裂纹将引起源极漏极阻抗的增加，并导致HEMT和包含它们的MMIC的性能和可靠性降级。 本发明通过将沟道区域长轴对准某一方向，使得沟道区域长轴与至少一种类型的微裂纹的轴线成直角，从而为HEMT提供了不需要的微裂纹的最小化效果。

公开(公告)号：US08759877B2

公开(公告)日：2014-06-24

申请号：US12802152

申请日：2010-06-01

申请人： Ishiang Shih ,  Cindy Xing Qiu ,  Chunong Qiu ,  Yi-Chi Shih

发明人： Ishiang Shih ,  Cindy Xing Qiu ,  Chunong Qiu ,  Yi-Chi Shih

IPC分类号： H01L29/66 ,  H01L29/20 ,  H01L29/778

CPC分类号： H01L29/2003 ,  H01L29/0603 ,  H01L29/0653 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/0843 ,  H01L29/1004 ,  H01L29/42316 ,  H01L29/42372 ,  H01L29/7371 ,  H01L29/7787

摘要： This invention teaches stress release metal electrodes for gate, drain and source in a field effect transistor and stress release metal electrodes for emitter, base and collector in a bipolar transistor. Due to the large difference in the thermal expansion coefficients between semiconductor materials and metal electrodes, significant strain and stresses can be induced in the devices during the fabrication and operation. The present invention provides metal electrode with stress release structures to reduce the strain and stresses in these devices.

公开(公告)号：US08455312B2

公开(公告)日：2013-06-04

申请号：US13199816

申请日：2011-09-12

申请人： Cindy X. Qiu ,  Ishiang Shih ,  Chunong Qiu ,  Yi-Chi Shih ,  Julia Qiu

发明人： Cindy X. Qiu ,  Ishiang Shih ,  Chunong Qiu ,  Yi-Chi Shih ,  Julia Qiu

IPC分类号： H01L21/338 ,  H01L21/44

CPC分类号： H01L21/0272 ,  H01L21/0274 ,  H01L21/28587 ,  H01L21/28593

摘要： In high frequency circuits, the switching speed of devices is often limited by the series resistance and capacitance across the input terminals. To reduce the resistance and capacitance, the cross-section of input electrodes is made into a T-shape or inverted L-shape through lithography. The prior art method for the formation of cavities for T-gate or inverted L-gate is achieved through several steps using multiple photomasks. Often, two or even three different photoresists with different sensitivity are required. In one embodiment of the present invention, an optical lithography method for the formation of T-gate or inverted L-gate structures using only one photomask is disclosed. In another embodiment, the structure for the T-gate or inverted L-gate is formed using the same type of photoresist material.

公开(公告)号：US20100301340A1

公开(公告)日：2010-12-02

申请号：US12455290

申请日：2009-06-01

申请人： Ishiang Shih ,  Cindy X. Qiu ,  Chunong Qiu ,  Yi-Chi Shih

发明人： Ishiang Shih ,  Cindy X. Qiu ,  Chunong Qiu ,  Yi-Chi Shih

IPC分类号： H01L27/088 ,  H01L29/786

CPC分类号： H01L29/78609 ,  H01L29/4908

摘要： Thin film transistors and arrays having controlled threshold voltage and improved ION/IOFF ratio are provided in this invention. In one embodiment, a thin film transistor having a first gate insulator of high breakdown field with positive fixed charges and a second gate insulator with negative fixed charges is provided; said negative fixed charges substantially compensate said positive fixed charges in order to reduce threshold voltage and OFF state threshold voltage of said transistor. In another embodiment, a thin film transistor having a first passivation layer with negative fixed charges is provided, the negative charges reduce substantially unwanted negative charges in the adjacent active channel and hence reduce the OFF state current and increase ION/IOFF ratio, which in turn reduce the threshold voltage of the transistor.

摘要翻译： 在本发明中提供具有受控阈值电压和改善的ION / IOFF比的薄膜晶体管和阵列。 在一个实施例中，提供具有具有正固定电荷的高击穿场的第一栅极绝缘体和具有负固定电荷的第二栅极绝缘体的薄膜晶体管; 所述负固定电荷基本上补偿所述正固定电荷，以便降低所述晶体管的阈值电压和OFF状态阈值电压。 在另一个实施例中，提供了具有负固定电荷的第一钝化层的薄膜晶体管，负电荷在相邻的有源沟道中减少了基本上不需要的负电荷，并因此降低了关闭状态电流并增加了ION / IOFF比， 降低晶体管的阈值电压。

公开(公告)号：US07211825B2

公开(公告)日：2007-05-01

申请号：US10866267

申请日：2004-06-14

申请人： Yi-Chi Shih ,  Cindy Xing Qiu ,  Ishiang Shih ,  Chunong Qiu

发明人： Yi-Chi Shih ,  Cindy Xing Qiu ,  Ishiang Shih ,  Chunong Qiu

IPC分类号： H01L29/04 ,  H01L29/15 ,  H01L29/10 ,  H01L31/00 ,  H01L31/036

CPC分类号： H01L29/7869 ,  H01L29/78633 ,  H01L29/78645 ,  H01L29/78648

摘要： In electronic displays or imaging units, the control of pixels is achieved by an array of transistors. These transistors are in a thin film form and arranged in a two-dimensional configuration to form switching circuits, driving circuits or even read-out circuits. In this invention, thin film transistors and circuits with indium oxide-based channel layers are provided. These thin film transistors and circuits may be fabricated at low temperatures on various substrates and with high charge carrier mobilities. In addition to conventional rigid substrates, the present thin film transistors and circuits are particularly suited for the fabrication on flexible and transparent substrates for electronic display and imaging applications. Methods for the fabrication of the thin film transistors with indium oxide-based channels are provided.

摘要翻译： 在电子显示器或成像单元中，通过晶体管阵列来实现像素的控制。 这些晶体管是薄膜形式并且被布置成二维配置以形成开关电路，驱动电路或甚至读出电路。 在本发明中，提供了具有氧化铟基沟道层的薄膜晶体管和电路。 这些薄膜晶体管和电路可以在各种基板上的低温下制造，并具有高电荷载流子迁移率。 除了传统的刚性衬底之外，本发明的薄膜晶体管和电路特别适用于用于电子显示和成像应用的柔性和透明衬底上的制造。 提供了制造具有基于氧化铟的通道的薄膜晶体管的方法。

公开(公告)号：US06363605B1

公开(公告)日：2002-04-02

申请号：US09433318

申请日：1999-11-03

申请人： Yi-Chi Shih ,  Long Q. Bui ,  Tsuneo C. Shishido

发明人： Yi-Chi Shih ,  Long Q. Bui ,  Tsuneo C. Shishido

IPC分类号： H01P1100

CPC分类号： H01P11/00 ,  Y10S29/016 ,  Y10T29/49016 ,  Y10T29/49018 ,  Y10T29/49052 ,  Y10T29/49064

摘要： A method for fabricating precision non-symmetrical L-shape waveguide end-launching probe for launching microwave signals in both vertical and horizontal polarizations is disclosed. The L-shape waveguide probe is in a form of thin plate, has a first arm and a second arm, and is precisely fabricated and attached to one end of the central metal pin of a feedthrough. The feedthrough is installed to an aperture formed in a major wall of the universal conductive housing to achieve hermetic sealing. The L-shape waveguide probe is aligned by means of a specially designed alignment tool so that long axis of the second arm is always perpendicular to the broad walls of the output waveguide, which is mounted to the universal housing with the broad walls of the output waveguide either horizontally or vertically. Hence, in this invention, an end-launching arrangement using the L-shape probes that could yield a flexible waveguide interface either in horizontal polarization or vertical polarization is provided. The impedance matching and frequency bandwidth may be adjusted by controlling dimensions and positions of the L-shape probe. A plurality of the thin plate L-shape waveguide probes is fabricated by a micro lithography and etching method to ensure reproducibility and reliability. By incorporating with an impedance transformation section having a slot, broad band performance is achieved using the L-shape waveguide probe.

摘要翻译： 公开了一种用于在垂直和水平偏振中发射微波信号的精确非对称L形波导终端探测器的制造方法。 L型波导探针是薄板形式，具有第一臂和第二臂，并精确地制造并附接到馈通的中心金属销的一端。 馈通被安装到形成在通用导电壳体的主壁中的孔以实现气密密封。 L型波导探针通过特别设计的对准工具对准，使得第二臂的长轴总是垂直于输出波导的宽壁，其输出波导壁安装到通用壳体 波导水平或垂直。 因此，在本发明中，提供了使用可以在水平极化或垂直极化中产生柔性波导接口的L形探针的终端发射装置。 可以通过控制L形探针的尺寸和位置来调整阻抗匹配和频率带宽。 通过微光刻和蚀刻方法制造多个薄板L形波导探针，以确保重现性和可靠性。 通过与具有时隙的阻抗变换部分结合，使用L形波导探针实现宽带性能。

公开(公告)号：US5283452A

公开(公告)日：1994-02-01

申请号：US837448

申请日：1992-02-14

申请人： Yi-Chi Shih ,  David C. Wang ,  Huy M. Le ,  Vincent Hwang ,  Tom Y. Chi

发明人： Yi-Chi Shih ,  David C. Wang ,  Huy M. Le ,  Vincent Hwang ,  Tom Y. Chi

IPC分类号： H01L29/417 ,  H01L29/812

CPC分类号： H01L29/41758

摘要： A distributed cell field-effect transistor (FET) amplifier (40) includes a plurality of parallel, elongated source (46a) and drain (46b) regions of individual FET unit cells (46) formed in a substrate (42) in transverse alternating relation, with a plurality of elongated channel regions (46c) being formed between and parallel to adjacent source (46a) and drain (46b) regions respectively. A source foot (48) and a drain foot (50) extend perpendicular to the source (46a) and drain (46b) regions on opposite longitudinally spaced sides thereof respectively. A gate foot (52) extends parallel to the source (48) and drain (50) feet, between the source foot (48) and the cells (46). Source (54) and drain (56) pads and gate (58) fingers extend from the source (48), drain (50) and gate (52) feet into electrical connection with the respective source (46a), drain (46b) and gate ( 46c) regions respectively. The source pads (54) include airbridge portions (54b) which extend over the gate foot (52) without making contact therewith. A fixed tuning circuit (70) is connected between the gate foot (52) and source foot (48), including an inductive stub (72) having a first end connected to the gate foot (52) and a second end, and a capacitor (74) having a first plate (74a) which is integral with the source foot (48) and a second plate connected to the second end of the stub (72). The integration of the capacitor (74) with the source foot (48) enables the amplifier (40) to be tuned at the gate foot (52), thereby eliminating undesirable coupling effects and the need for a separate via for the tuning circuit (70).

摘要翻译： 分布式单元场效应晶体管（FET）放大器（40）包括以横向交替关系形成在基板（42）中的单个FET单元（46）的多个平行细长源（46a）和漏极（46b） ，其中多个细长沟道区（46c）分别形成在平行于相邻源（46a）和漏极（46b）之间并且平行于漏极（46b）区域。 源脚（48）和排水脚（50）分别垂直于源（46a）和相对的纵向间隔开的排出（46b）区域延伸。 门脚（52）平行于源脚（48）和细胞（46）之间的源极（48）和漏极（50）脚延伸。 源极（54）和漏极（56）焊盘和栅极（58）指状物从源极（48），漏极（50）和栅极（52）脚延伸到与相应源极（46a），漏极（46b）和 门（46c）区域。 源极焊盘（54）包括在栅极（52）上延伸而不与其接触的气桥部分（54b）。 固定调谐电路（70）连接在栅极脚（52）和源脚（48）之间，包括具有连接到栅极脚（52）的第一端和第二端的电感短截线（72），以及电容器 （74）具有与源脚（48）成一体的第一板（74a）和连接到短截线（72）的第二端的第二板。 电容器（74）与源极（48）的集成使得放大器（40）能够在栅极脚（52）处被调谐，从而消除不期望的耦合效应，并且需要用于调谐电路（70）的单独的通孔 ）。