Abstract:
An organic light emitting diode pixel compensation method, an organic light emitting diode pixel compensation device and a display device are provided. The organic light emitting diode pixel compensation method includes: testing drive transistors of sub-pixels in an Nth row to obtain first test information; testing drive transistors of sub-pixels in an Mth row to obtain second test information; calculating a compensation parameter based on the first test information and the second test information; and compensating the sub-pixels in the Nth row, the sub-pixels in the Mth row and the sub-pixels in a rows adjacent to the Nth row and the Mth row based on the compensation parameter, where N=an+b, M=an+c, a≥2, 0≤b
Abstract:
A pixel circuit is disclosed which includes a plurality of sub-pixel circuits each including: an organic light emitting diode having an anode; a driving transistor connected in series with the organic light emitting diode via the anode; and a sensing transistor having a first electrode connected to the anode, a gate connected to a first scan line, and a second electrode. The pixel circuit further includes a common transistor having a first electrode connected to the second electrodes of the sensing transistors of the plurality of sub-pixel circuits, a gate connected to the first scan line, and a second electrode connected to a sensing line. Also disclosed is a display apparatus including the pixel circuit and a method of driving the pixel circuit.
Abstract:
The present invention provides a pixel circuit, a driving method thereof, an array substrate, and a display device. The pixel circuit comprises: a reset unit, configured to output a reference signal; a data writing unit, configured to output a data signal; a compensation unit, which is connected to the reset unit and the data writing unit as well as an output node, and receives a power voltage signal, and a light-emitting unit, which is connected to the output node and a cathode of a power supply and configured to emit light under the drive of the light emission drive signal in a light emission phase.
Abstract:
A shift register is provided to include: a voltage regulating circuit to adjust voltages at first and second nodes; a light-emitting cascade output circuit to write a second operating voltage from a second power terminal to a light-emitting cascade signal output terminal in response to control of the voltage at the first node, and write a first operating voltage from a first power terminal to the light-emitting cascade signal output terminal in response to control of the voltage at the second node; a light-emitting driving output circuit to write a third operating voltage from a third power terminal to a light-emitting control driving signal output terminal in response to control of the voltage at the first node, and write a fifth operating voltage from a fifth power terminal to the light-emitting control driving signal output terminal in response to control of the voltage at the second node; and a first anti-leakage circuit to write a fourth operating voltage from a fourth power terminal to a first anti-leakage node in response to control of the voltage at the second node.
Abstract:
A display substrate includes an underlayer substrate and a circuit structure layer. The circuit structure layer is located in a display area of the underlayer substrate. The circuit structure layer includes at least one first circuit area and at least one second circuit area. The first circuit area includes at least one first gate drive circuit; the second circuit area includes at least one second gate drive circuit. The first gate drive circuit is cascaded with the second gate drive circuit. The first gate drive circuit includes a plurality of cascaded first gate drive units, and the second gate drive circuit includes a plurality of cascaded second gate drive units. A plurality of first gate drive units are sequentially arranged in a second direction, and a plurality of second gate drive units are sequentially arranged in the second direction.
Abstract:
Provided is a pixel drive circuit. The pixel drive circuit includes a plurality of scan drive circuits transmitting gate drive signals to pixels, a plurality of emission drive circuits transmitting emission control signals to the pixels, a plurality of compensation drive circuits transmitting compensation signals to the pixels, and a plurality of reset drive circuits transmitting reset signals to the pixels, which are all cascaded in a pixel column direction. In addition, the scan drive circuit, the emission drive circuit, the compensation drive circuit, and the reset drive circuit corresponding to the same row of pixels are arranged sequentially along a pixel row direction, the scan drive circuit being disposed farthest away from the pixels. Moreover, among signal lines coupled to the pixel drive circuit, a plurality of signal lines is overlapped with each other, and cutouts are provided at the overlapping portions of the plurality of signal lines.
Abstract:
A display substrate and a display device, the display substrate includes a base substrate, a pixel driving circuit layer, a first planarization layer, a first metal layer, a second planarization layer, a plurality of first electrodes and a pixel definition layer; the pixel driving circuit layer includes a plurality of pixel driving circuits, the first planarization layer includes a plurality of first vias respectively exposing output terminals of the pixel driving circuits, the first metal layer includes a plurality of data lines extending in a first direction, the pixel definition layer includes a plurality of first definition walls extending in the first direction and a plurality of second definition walls extending in a second direction, and an orthographic projection of at least part of the data lines on the base substrate respectively overlaps with orthographic projections of the plurality of first definition walls on the base substrate.
Abstract:
A driving circuit, a driving method and a display device are provided. The driving circuit includes a first control node control circuit, a second control node control circuit, a first node control circuit and a second node control circuit, wherein, the first control node control circuit is configured to control a potential of the first control node; the second control node control circuit is configured to control a potential of the second control node; the first node control circuit is configured to control a potential of the first node; the second node control circuit is electrically connected to the second control node, a first clock signal terminal and a second node respectively, and is configured to control to connect the first clock signal terminal and the second node under the control of the potential of the second control node.
Abstract:
A display panel has a display region, a fan-out region located on a side of the display region, and a bonding region located on a side of the fan-out region away from the display region. The display panel includes a gate driving circuit disposed in the display region, a plurality of data lines and a plurality of control signal lines that all extends from the display region to the fan-out region, and a plurality of data fan-out leads and a plurality of first fan-out leads that are all disposed in the fan-out region. Each data line is electrically connected to a data fan-out lead. The data fan-out leads are gathered to the bonding region. The control signal lines are electrically connected to the gate driving circuit. Each control signal line is electrically connected to a first fan-out lead. The first fan-out leads are gathered to the bonding region.
Abstract:
A display substrate includes: a base substrate; a plurality of pixel circuits on the base substrate; and a plurality of pixels; the pixel includes a first sub-pixel, a second sub-pixel and a third sub-pixel; orthographic projections of the first sub-pixel, the second sub-pixel and the third sub-pixel on the base substrate do not overlap with each other; the first sub-pixel, the second sub-pixel and the third sub-pixel are electrically connected to the pixel circuits in a one-to-one correspondence manner; a first distance in a first direction exists between the first sub-pixel and the second sub-pixel, and a first via is arranged in the first distance; a second distance in the first direction exists between the first sub-pixel and the third sub-pixel, and a first via is arranged in the second distance; a third distance in the first direction exists between the second sub-pixel and the third sub-pixel.