公开(公告)号：US06459331B1

公开(公告)日：2002-10-01

申请号：US09146035

申请日：1998-09-02

申请人： Hideki Takeuchi ,  Masami Murakata ,  Masaaki Yamada ,  Reiko Nojima ,  Takashi Ishioka ,  Mutsunori Igarashi

发明人： Hideki Takeuchi ,  Masami Murakata ,  Masaaki Yamada ,  Reiko Nojima ,  Takashi Ishioka ,  Mutsunori Igarashi

IPC分类号： H03K500

CPC分类号： H03K19/00361 ,  H03K17/162

摘要： A noise suppression circuit encompasses an internal circuit, a bypass capacitor, first and second transistors. The internal circuit has high and low level terminals, and the low level terminal is connected to a low level power supply line. The internal circuit is supplied with enable and inverted enable signals. The first transistor has a first control electrode, and one main electrode is connected to the high level terminal. The first control electrode is supplied with the inverted enable signal. The bypass capacitor is connected between the other main electrode of the first transistor and the low level power supply line. The second transistor is connected between the other main electrode of the first transistor and a high level power supply line. The second transistor has a second control electrode supplied with the enable signal. The second transistor is not conductive when the internal circuit is active.

摘要翻译： 噪声抑制电路包括内部电路，旁路电容器，第一和第二晶体管。 内部电路具有高低电平端子，低电平端子连接到低电平电源线。 内部电路提供使能和反相使能信号。 第一晶体管具有第一控制电极，一个主电极连接到高电平端子。 第一控制电极被提供有反相使能信号。 旁路电容器连接在第一晶体管的另一个主电极和低电平电源线之间。 第二晶体管连接在第一晶体管的另一个主电极和高电平电源线之间。 第二晶体管具有提供有使能信号的第二控制电极。 内部电路激活时，第二个晶体管不导通。

公开(公告)号：US06223333B1

公开(公告)日：2001-04-24

申请号：US08882495

申请日：1997-06-25

申请人： Mototaka Kuribayashi ,  Hideki Takeuchi ,  Junichi Tsujimoto

发明人： Mototaka Kuribayashi ,  Hideki Takeuchi ,  Junichi Tsujimoto

IPC分类号： G06F1750

CPC分类号： G06F17/5031

摘要： In the timing analysis method, connection information is compared to circuit patterns that have been stored in a memory in advance after reading the connection information of an electrical circuit, a connection information supplement process to supplement vertically circuit connection information regarding the matched circuit pattern for the stored connection information is performed when the connection information is matched with one of the registered circuit patterns, and a timing analysis of the connection information that has been supplemented by the connection information supplement process is executed.

摘要翻译： 在定时分析方法中，连接信息在读取电路的连接信息之后，预先与存储在存储器中的电路图案进行比较，连接信息补充处理用于补充垂直电路关于匹配电路图案的连接信息 当连接信息与注册的电路图案中的一个匹配时执行存储的连接信息，并且执行已经由连接信息补充处理补充的连接信息的定时分析。

公开(公告)号：US6083273A

公开(公告)日：2000-07-04

申请号：US715365

申请日：1996-09-12

申请人： Hideki Takeuchi

发明人： Hideki Takeuchi

IPC分类号： G01R31/28 ,  G06F17/50 ,  H01L21/82

CPC分类号： G06F17/5031

摘要： A circuit is constructed on transistor level out of a net list and it is determined if the output node of a circuit for receiving a clock signal can go to a high impedance state from this circuit. If the output node can go to a high impedance state, it is designated as the starting point for a path searching operation and an input node of the circuit not receiving a clock signal is designated as the terminating point of the path searching operation. If, on the other hand, the output node cannot go to a high impedance state, the output node is designated as the clock node and an input node of the circuit not receiving a clock signal is designated as the terminating point of the path searching operation. With this arrangement, a sequential circuit can be divided into combinational circuits for certain.

摘要翻译： 电路在网络列表中的晶体管级上构成，并且确定用于接收时钟信号的电路的输出节点是否可以从该电路进入高阻抗状态。 如果输出节点可以进入高阻抗状态，则将其指定为路径搜索操作的起始点，并且将未接收到时钟信号的电路的输入节点指定为路径搜索操作的终止点。 另一方面，如果输出节点不能进入高阻抗状态，则输出节点被指定为时钟节点，并且未接收时钟信号的电路的输入节点被指定为路径搜索操作的终止点 。 通过这种布置，可以将顺序电路分成若干组合电路。

公开(公告)号：US5305458A

公开(公告)日：1994-04-19

申请号：US518411

申请日：1990-05-02

申请人： Yukihiro Motomura ,  Hideki Takeuchi ,  Hideo Sawamoto ,  Mari Ara

发明人： Yukihiro Motomura ,  Hideki Takeuchi ,  Hideo Sawamoto ,  Mari Ara

IPC分类号： G06F12/10 ,  G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0292

摘要： In a multiple virtual storage system and more particularly in an address control apparatus, there are provided two kinds of holding devices a designation holding device for holding a segment table designations in association with access registers and a translation buffer for holding translation pairs of the access register and segment table designation. With this arrangement, the segment table designation designating the virtual address space possessing an operand of an instruction can be supplied quickly and efficiently.

摘要翻译： 在多虚拟存储系统中，特别是在地址控制装置中，提供了两种保持装置：用于保存与访问寄存器相关联的分段表名称的指定保存装置和用于保存访问寄存器的转换对的转换缓冲器 和分段表指定。 通过这种布置，可以快速有效地提供指定具有指令的操作数的虚拟地址空间的段表指定。

公开(公告)号：US5299164A

公开(公告)日：1994-03-29

申请号：US21515

申请日：1993-02-23

申请人： Hideki Takeuchi ,  Shigeyuki Hayakawa ,  Tomoaki Yabe

发明人： Hideki Takeuchi ,  Shigeyuki Hayakawa ,  Tomoaki Yabe

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/84

摘要： An internal row address signal output from an address buffer is supplied to first and second row partial decoders. A programming circuit is programmed to store information indicating whether the redundant function is used or not and a defective address corresponding to a defective main word line or defective memory cell in a main memory cell array. The defective row address and the internal row adders signal are compared with each other by the programming circuit and the spare decoder, a control signal corresponding to the coincidence/non-coincidence of the compared row addresses is output, and a partial decode signal of the internal row address signal is output when the compared row addresses coincide with each other. The second partial decoder receives a control signal output from the spare decoder and outputs a partial decode signal of the internal row address signal when the control signal indicates the non-coincidence of the compared row addresses. The partial decode signals output from the first and second row partial decoders are supplied to the main row decoder which in turn selects one of main word lines in the main memory cell array. The partial decode signal output from the spare decoder is supplied to a spare row decoder which in turn selects one of spare word lines in a spare memory cell array.

摘要翻译： 从地址缓冲器输出的内部行地址信号被提供给第一和第二行部分解码器。 编程电路被编程为存储指示是否使用冗余功能的信息以及与主存储单元阵列中的有缺陷的主字线或有缺陷的存储单元相对应的缺陷地址。 通过编程电路和备用解码器将有缺陷的行地址和内部行加法器信号相互比较，输出与比较的行地址的一致/非重合相对应的控制信号，并且输出 当比较的行地址彼此一致时，输出内部行地址信号。 当控制信号指示比较的行地址的不一致时，第二部分解码器接收从备用解码器输出的控制信号并输出​​内部行地址信号的部分解码信号。 从第一和第二行部分解码器输出的部分解码信号被提供给主行解码器，主行解码器依次选择主存储单元阵列中的一个主字线。 从备用解码器输出的部分解码信号被提供给备用行解码器，备用行解码器又选择备用存储单元阵列中的一个备用字线。

公开(公告)号：US4048275A

公开(公告)日：1977-09-13

申请号：US627409

申请日：1975-10-30

申请人： Teruyoshi Usamoto ,  Kenji Miyawaki ,  Toshiaki Shiota ,  Hideki Takeuchi ,  Yoshio Tadokoro

发明人： Teruyoshi Usamoto ,  Kenji Miyawaki ,  Toshiaki Shiota ,  Hideki Takeuchi ,  Yoshio Tadokoro

IPC分类号： C08J9/06 ,  B29C37/00 ,  B29C43/00 ,  B29C44/42 ,  B29C45/00 ,  B29C45/23 ,  B29C45/62 ,  B29D27/00 ,  B29F1/08

CPC分类号： B29C44/42 ,  Y10S264/05 ,  Y10S264/18 ,  Y10S264/83

摘要： An injection molding process for forming cross-linked, foamed moldings of an ethylenic polymer by passing a molding composition comprising an ethylenic polymer/cross-linking agent/foaming agent blend through the cylinder of an injection molding machine without substantially decomposing the cross-linking agent and the foaming agent, introducing the molding composition into a molding composition holding chamber provided at the exit end of the cylinder of the injection molding machine to decompose the cross-linking agent and the foaming agent therein, and injecting the molding composition into a mold.The invention also provides apparatus for carrying out the process comprising an injection molding cylinder for conveying and plasticizing the molding composition and a molding composition holding chamber provided at the exit end of the cylinder.

摘要翻译： 一种用于通过使包含乙烯性聚合物/交联剂/发泡剂混合物的模塑组合物通过注射成型机的圆筒通过而形成交联的乙烯类聚合物的发泡模制品的注射成型方法，而基本上不分解交联剂 和发泡剂，将成型组合物引入设置在注射成型机的圆筒的出口端的成型组合物保持室中，以将交联剂和发泡剂分解，并将模塑组合物注入模具中。