-
公开(公告)号:US11495552B2
公开(公告)日:2022-11-08
申请号:US16024702
申请日:2018-06-29
Applicant: Intel Corporation
Inventor: Aleksandar Aleksov , Thomas Sounart , Kristof Darmawikarta , Henning Braunisch , Prithwish Chatterjee , Andrew J. Brown
IPC: H01L23/64 , H01L23/498 , H01L21/48 , H01L23/00
Abstract: Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.
-
公开(公告)号:US11387187B2
公开(公告)日:2022-07-12
申请号:US16021966
申请日:2018-06-28
Applicant: Intel Corporation
Inventor: Andrew Paul Collins , Jianyong Xie , Sujit Sharan , Henning Braunisch , Aleksandar Aleksov
IPC: H01L23/495 , H01L23/053 , H01L23/48 , H01L21/4763 , H01L23/538 , H01L25/065 , H01L21/48 , H01L23/498 , H01L23/522 , H01L21/768 , H01L23/528 , H01L25/07
Abstract: Embodiments may relate to an interposer that has a first layer with a plurality of first layer pads that may couple with a die. The interposer may further include a second layer with a power delivery component. The interposer may further include a very high density (VHD) layer, that has a VHD pad coupled by a first via with the power delivery component and coupled by a second via with a first layer pad. Other embodiments may be described and/or claimed.
-
63.
公开(公告)号:US11380624B2
公开(公告)日:2022-07-05
申请号:US16651949
申请日:2017-09-30
Applicant: Intel Corporation
Inventor: Feras Eid , Henning Braunisch , Shawna M. Liff , Georgios C. Dogiamis , Johanna M. Swan
IPC: H01L23/552 , H01L21/48 , H01L23/04 , H01L23/10 , H01L23/498 , H01L23/00
Abstract: A device package and a method of forming the device package are described. The device package includes a substrate having a ground plane and dies disposed on the substrate. The dies are electrically coupled to the substrate with solder balls or bumps surrounded by an underfill layer. The device package has a mold layer disposed over and around the dies, the underfill layer, and the substrate. The device package further includes an additively manufactured electromagnetic interference (EMI) shield layer disposed on an outer surface of the mold layer. The additively manufactured EMI shield layer is electrically coupled to the ground plane of the substrate. The outer surface of the mold layer may include a topmost surface and one or more sidewalls that are covered with the additively manufactured EMI shield layer. The additively manufactured EMI shield may include a first and second additively manufactured EMI shield layers and an additively manufactured EMI shield frame.
-
公开(公告)号:US11222847B2
公开(公告)日:2022-01-11
申请号:US16469084
申请日:2016-12-28
Applicant: Intel Corporation
Inventor: Ravindranath V. Mahajan , Zhiguo Qian , Henning Braunisch , Kemal Aygun , Sujit Sharan
IPC: H01L23/538 , H01L25/065
Abstract: A device and method of utilizing a repeater circuit to extend the viable length of an interconnect bridge. Integrated circuit packages using a repeater circuit in a repeater die, embedded in a substrate, and included in an interconnect bridge are show. Methods of connecting semiconductor dies using interconnect bridges coupled with repeater circuits are shown.
-
公开(公告)号:US20210408657A1
公开(公告)日:2021-12-30
申请号:US16912067
申请日:2020-06-25
Applicant: Intel Corporation
Inventor: Diego Correas-Serrano , Georgios Dogiamis , Henning Braunisch , Neelam Prabhu Gaunkar , Telesphor Kamgaing
IPC: H01P5/02 , H01L23/498 , H01R12/75 , H01L23/66 , H01P3/16
Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.
-
公开(公告)号:US20210408652A1
公开(公告)日:2021-12-30
申请号:US16911559
申请日:2020-06-25
Applicant: Intel Corporation
Inventor: Diego Correas-Serrano , Georgios Dogiamis , Henning Braunisch , Neelam Prabhu Gaunkar , Telesphor Kamgaing
Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.
-
公开(公告)号:US20210358855A1
公开(公告)日:2021-11-18
申请号:US17388964
申请日:2021-07-29
Applicant: Intel Corporation
Inventor: Veronica Strong , Aleksandar Aleksov , Henning Braunisch , Brandon Rawlings , Johanna Swan , Shawna Liff
Abstract: An integrated circuit package may be formed including at least one die side integrated circuit device having an active surface electrically attached to an electronic interposer, wherein the at least one die side integrated circuit device is at least partially encased in a mold material layer and wherein a back surface of the at least one die side integrated circuit device is in substantially the same plane as an outer surface of the mold material layer. At least one stacked integrated circuit device may be electrically attached to the back surface of the at least one die side integrated circuit through an interconnection structure formed between the at least one die side integrated circuit device and the at least one stacked integrated circuit device.
-
公开(公告)号:US11101205B2
公开(公告)日:2021-08-24
申请号:US16564168
申请日:2019-09-09
Applicant: Intel Corporation
Inventor: Johanna Swan , Henning Braunisch , Aleksandar Aleksov , Shawna Liff , Brandon Rawlings , Veronica Strong
IPC: H01L23/498 , G03F1/38 , G03F1/54 , G03F1/68
Abstract: An lithographic reticle may be formed comprising a transparent substrate, a substantially opaque mask formed on the transparent substrate that defines at least one exposure window, wherein the at least one exposure window has a first end, a first filter formed on the transparent substrate within the at least one exposure window and abutting the first end thereof, and a second filter formed on the transparent substrate within the at least one exposure window and abutting the first filter, wherein an average transmissivity of the first filter is substantially one half of a transmissivity of the second filter. In another embodiment, the at least one exposure window includes a third filter abutting the second end and is adjacent the second filter. Further embodiments of the present description include interconnection structures and systems fabricated using the lithographic reticle.
-
公开(公告)号:US10998272B2
公开(公告)日:2021-05-04
申请号:US16573943
申请日:2019-09-17
Applicant: Intel Corporation
Inventor: Aleksandar Aleksov , Henning Braunisch , Shawna Liff , Brandon Rawlings , Veronica Strong , Johanna Swan
IPC: H01L23/538 , H01L23/00 , H01L23/498
Abstract: An electronic interposer may be formed using organic material layers, while allowing for the fabrication of high density interconnects within the electronic interposer without the use of embedded silicon bridges. This is achieved by forming the electronic interposer in three sections, i.e. an upper section, a lower section and a middle section. The middle section may be formed between the upper section and the lower section, wherein a thickness of each layer of the middle section is thinner than a thickness of any of the layers of the upper section and the lower section, and wherein conductive routes within the middle section have a higher density than conductive routes within the upper section and the lower section.
-
公开(公告)号:US10992342B2
公开(公告)日:2021-04-27
申请号:US16483019
申请日:2017-03-01
Applicant: Intel Corporation
Inventor: Yidnekachew S. Mekonnen , Kemal Aygun , Henning Braunisch
Abstract: Technology for simplified multimode signaling includes determining first and second self α-terms, cross coupling α-terms, and a delay skew term. For each communication link bundled in groups, the signals can be modulated as a superposition of the signals delayed and weighted based on the first and second self α-terms, the cross coupling α-terms and the delay skew term.
-
-
-
-
-
-
-
-
-