公开(公告)号：US20240232122A1

公开(公告)日：2024-07-11

申请号：US18613256

申请日：2024-03-22

Applicant: Intel Corporation

Inventor： Andrew Paul Collins ,  Mahesh Krishnappayya Kumashikar ,  Srikanth Nimmagadda

IPC: G06F13/42 ,  G06F9/38 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F9/3822 ,  G06F9/3869 ,  G06F9/3877 ,  G06F13/4027

Abstract: Embodiments may relate to a microelectronic assembly including a substrate; a first die electrically coupled to the substrate, wherein the first die includes a first edge, a second edge, a third edge opposite the first edge, and a fourth edge opposite the second edge; and a second die electrically coupled to the substrate adjacent to the second edge of the first die and communicatively coupled to the first die, wherein the second die includes a fifth edge and a sixth edge opposite the fifth edge, and wherein the fifth edge of the second die is substantially aligned with the first edge of the first die and the sixth edge of the second die extends beyond the third edge of the first die, where the first die includes a processor die and the second die includes an input/output (I/O) die.

公开(公告)号：US20230081139A1

公开(公告)日：2023-03-16

申请号：US17475726

申请日：2021-09-15

Applicant: Intel Corporation

Inventor： Krishna Vasanth Valavala ,  Chandra Mohan Jha ,  Andrew Paul Collins ,  Omkar G. Karhade

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L23/367 ,  H01L25/00

Abstract: An example microelectronic assembly includes a substrate, a bridge die over the substrate, and a die stack between the substrate and the bridge die, the die stack including a logic die and at least one memory die, where the logic die is between the at least one memory die and the bridge die.

公开(公告)号：US20200006236A1

公开(公告)日：2020-01-02

申请号：US16021966

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Andrew Paul Collins ,  Jianyong Xie ,  Sujit Sharan ,  Henning Braunisch ,  Aleksandar Aleksov

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L25/065

Abstract: Embodiments may relate to an interposer that has a first layer with a plurality of first layer pads that may couple with a die. The interposer may further include a second layer with a power delivery component. The interposer may further include a very high density (VHD) layer, that has a VHD pad coupled by a first via with the power delivery component and coupled by a second via with a first layer pad. Other embodiments may be described and/or claimed.

公开(公告)号：US11387187B2

公开(公告)日：2022-07-12

申请号：US16021966

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Andrew Paul Collins ,  Jianyong Xie ,  Sujit Sharan ,  Henning Braunisch ,  Aleksandar Aleksov

IPC: H01L23/495 ,  H01L23/053 ,  H01L23/48 ,  H01L21/4763 ,  H01L23/538 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L25/07

Abstract: Embodiments may relate to an interposer that has a first layer with a plurality of first layer pads that may couple with a die. The interposer may further include a second layer with a power delivery component. The interposer may further include a very high density (VHD) layer, that has a VHD pad coupled by a first via with the power delivery component and coupled by a second via with a first layer pad. Other embodiments may be described and/or claimed.

公开(公告)号：US20210263880A1

公开(公告)日：2021-08-26

申请号：US16799192

申请日：2020-02-24

Applicant: Intel Corporation

Inventor： Andrew Paul Collins ,  Mahesh Krishnappayya Kumashikar ,  Srikanth Nimmagadda

IPC: G06F13/42 ,  G06F9/38 ,  G06F13/40

Abstract: Embodiments may relate to a die with a processor. The die may include a first input/output (I/O) tile adjacent to a first side of the processor, and a second I/O tile adjacent to a second side of the processor. The first or second I/O tiles may be communicatively coupled with the processor. Other embodiments may be described or claimed.