公开(公告)号：US20190034203A1

公开(公告)日：2019-01-31

申请号：US15665212

申请日：2017-07-31

Applicant: INTEL CORPORATION

Inventor： Federico Ardanaz ,  Roger Gramunt ,  Jesus Corbal ,  Dennis R. Bradford ,  Jonathan M. Eastep

IPC: G06F9/30 ,  G05F1/10 ,  G06F1/32 ,  G06F9/38

Abstract: An apparatus is provided which comprises: a component; a voltage generator to supply load current to the component; first one or more circuitries to predict that the load current is to increase from a first time; and second one or more circuitries to, in anticipation of the increase in the load current from the first time, cause the component to execute first instructions during a time period that occurs prior to the first time.

公开(公告)号：US10133577B2

公开(公告)日：2018-11-20

申请号：US13997791

申请日：2012-12-19

Applicant: Intel Corporation

Inventor： Jesus Corbal ,  Dennis R. Bradford ,  Jonathan C. Hall ,  Thomas D. Fletcher ,  Brian J. Hickmann ,  Dror Markovich ,  Amit Gradstein

IPC: G06F1/32 ,  G06F9/30 ,  G06F9/38

Abstract: A processor includes an instruction schedule and dispatch (schedule/dispatch) unit to receive a single instruction multiple data (SIMD) instruction to perform an operation on multiple data elements stored in a storage location indicated by a first source operand. The instruction schedule/dispatch unit is to determine a first of the data elements that will not be operated to generate a result written to a destination operand based on a second source operand. The processor further includes multiple processing elements coupled to the instruction schedule/dispatch unit to process the data elements of the SIMD instruction in a vector manner, and a power management unit coupled to the instruction schedule/dispatch unit to reduce power consumption of a first of the processing elements configured to process the first data element.

公开(公告)号：US09715432B2

公开(公告)日：2017-07-25

申请号：US14581859

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Ramon Matas ,  Roger Gramunt ,  Chung-Lun Chan ,  Benjamin C. Chaffin ,  Aditya Kesiraju ,  Jonathan C. Hall ,  Jesus Corbal

IPC: G06F11/14 ,  G06F9/38

CPC classification number: G06F11/141 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/38 ,  G06F9/3859 ,  G06F9/3865

Abstract: Exemplary aspects are directed toward resolving fault suppression in hardware, which at the same time does not incur a performance hit. For example, when multiple instructions are executing simultaneously, a mask can specify which elements need not be executed. If the mask is disabled, those elements do not need to be executed. A determination is then made as to whether a fault happens in one of the elements that have been disabled. If there is a fault in one of the elements that has been disabled, a state machine re-fetches the instructions in a special mode. More specifically, the state machine determines if the fault is on a disabled element, and if the fault is on a disabled element, then the state machine specifies that the fault should be ignored. If during the first execution there was no mask, if there is an error present during execution, then the element is re-run with the mask to see if the error is a “real” fault.

公开(公告)号：US20170185379A1

公开(公告)日：2017-06-29

申请号：US14757942

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Cristina S. Anderson ,  Marius A. Cornea-Hasegan ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Nikita Astafev ,  Mark J. Charney ,  Milind B. Girkar ,  Amit Gradstein ,  Simon Rubanovich ,  Zeev Sperber

IPC: G06F7/487 ,  G06F7/499 ,  G06F7/485

CPC classification number: G06F7/4876 ,  G06F7/485 ,  G06F7/49915

Abstract: An example processor includes a register and a fused multiply-add (FMA) low functional unit. The register stores first, second, and third floating point (FP) values. The FMA low functional unit receives a request to perform an FMA low operation: multiplies the first FP value with the second FP value to obtain a first product value; adds the first product with the third FP value to generate a first result value; rounds the first result to generate a first FMA value; multiplies the first FP value with the second FP value to obtain a second product value; adds the second product value with the third FP value to generate a second result value; and subtracts the FMA value from the second result value to obtain a third result value, which can then be normalized and rounded (FMA low result) and sent the FMA low result to an application.

公开(公告)号：US20160266902A1

公开(公告)日：2016-09-15

申请号：US13977736

申请日：2011-12-16

Applicant: Intel Corporation

Inventor： Jesus Corbal ,  Andrew T. Forsyth ,  Lisa K. Wu ,  Thomas D. Fletcher

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30007 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/3836 ,  G06F15/8053 ,  G06F17/17 ,  G06T3/4007

Abstract: Instructions and logic provide vector linear interpolation functionality. In some embodiments, responsive to an instruction specifying: a first operand from a set of vector registers, a size of each of the vector elements, a portion of the vector elements upon which to compute linear interpolations, a second operand from a set of vector registers, and a third operand; an execution unit, reads a first, a second and a third value of the size of vector elements from corresponding data fields in the first, the second and the third operand respectively and computes an interpolated value as the first value multiplied by the second value minus the second value multiplied by the third value plus the third value.

Abstract translation: 指令和逻辑提供矢量线性插值功能。 在一些实施例中，响应于指令指定：来自一组向量寄存器的第一操作数，每个向量元素的大小，用于计算线性内插的向量元素的一部分，来自一组向量的第二操作数 寄存器和第三操作数; 执行单元分别从第一，第二和第三操作数中的对应数据字段读取向量元素的大小的第一值，第二和第三值，并计算内插值作为第一值乘以第二值减去 第二个值乘以第三个值加上第三个值。

公开(公告)号：US09442733B2

公开(公告)日：2016-09-13

申请号：US14966206

申请日：2015-12-11

Applicant: Intel Corporation

Inventor： Bret L. Toll ,  Robert Valentine ,  Jesus Corbal ,  Elmoustapha Ould-Ahmed-Vall ,  Mark J. Charney

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30189 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/30145

Abstract: Receive packed data operation mask comparison instruction indicating first packed data operation mask having first packed data operation mask bits and second packed data operation mask having second packed data operation mask bits. Each packed data operation mask bit of first mask corresponds to a packed data operation mask bit of second mask in corresponding position. Modify first flag to first value if bitwise AND of each packed data operation mask bit of first mask with each corresponding packed data operation mask bit of second mask is zero. Otherwise modify first flag to second value. Modify second flag to third value if bitwise AND of each packed data operation mask bit of first mask with bitwise NOT of each corresponding packed data operation mask bit of second mask is zero. Otherwise modify second flag to fourth value.

公开(公告)号：US09411592B2

公开(公告)日：2016-08-09

申请号：US13731005

申请日：2012-12-29

Applicant: INTEL CORPORATION

Inventor： Robert Valentine ,  Mark J. Charney ,  Jesus Corbal ,  Milind B. Girkar ,  Christopher J. Hughes ,  Elmoustapha Ould-Ahmed-Vall ,  Brett L. Toll

IPC: G06F9/30 ,  G06F9/38 ,  G06F7/60 ,  H03M7/20

CPC classification number: G06F9/30145 ,  G06F7/607 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3836 ,  G06F9/3887 ,  H03M7/20

Abstract: Instructions and logic provide SIMD address conflict resolution with vector population count functionality. Some embodiments include processors with a register with a variable plurality of data fields, each of the data fields to store a variable second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of bits set to one for corresponding data fields. Responsive to decoding a vector population count instruction, execution units count the number of bits set to one for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector population count instructions can be used with variable sized elements and conflict masks to generate iteration counts and completion masks to be used each iteration to resolve dependencies in gather-modify-scatter SIMD operations.

Abstract translation: 指令和逻辑提供SIMD地址冲突解决与向量群体计数功能。 一些实施例包括具有可变多个数据字段的寄存器的处理器，每个数据字段用于存储可变的第二多个位。 目的地寄存器具有对应的数据字段，这些数据字段中的每一个用于存储为相应的数据字段设置为1的位数的计数。 响应于对向量群体计数指令进行解码，执行单元对寄存器中的每个数据字段设置为1的位数进行计数，并将计数存储在第一目的地寄存器的相应数据字段中。 矢量人口计数指令可用于可变大小的元素和冲突掩码，以生成迭代计数和完成掩码，以便在每次迭代中使用以解决聚集修改散射SIMD操作中的依赖关系。

公开(公告)号：US20160179548A1

公开(公告)日：2016-06-23

申请号：US14580055

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  Robert Valentine ,  Jesus Corbal ,  Mark J. Charney

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30185 ,  G06F7/76 ,  G06F7/764 ,  G06F9/30018 ,  G06F9/30032

Abstract: In one embodiment a processing device implements a set of instructions to perform an inverse centrifuge operation using vector or general purpose registers. The inverse centrifuge operation interleaves bits from opposite regions of a source and writes the interleaved bits to a destination. The instructions use a control mask where each bit with a mask value of one is obtained from one side of the source register or vector elements with a mask of zero are obtained from the opposing side.

Abstract translation: 在一个实施例中，处理装置实现一组指令以使用向量或通用寄存器来执行逆离心机操作。 反向离心机操作从源的相对区域交错比特，并将交错比特写入目的地。 指令使用控制掩码，其中从源寄存器的一侧获得具有掩码值为1的每个位或从相对侧获得具有零掩蔽的向量元素。

公开(公告)号：US20250004716A1

公开(公告)日：2025-01-02

申请号：US18654951

申请日：2024-05-03

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Menachem ADELMAN ,  Milind B. GIRKAR ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Bret L. TOLL ,  Rinat RAPPOPORT ,  Jesus Corbal ,  Stanislav SHWARTSMAN ,  Dan BAUM ,  Igor YANOVER ,  Alexander F. HEINECKE ,  Barukh ZIV ,  Elmoustapha OULD-AHMED-VALL ,  Yuri GEBIL ,  Raanan SADE

IPC: G06F7/485 ,  G06F7/487 ,  G06F7/76 ,  G06F9/30 ,  G06F9/38 ,  G06F17/16

Abstract: Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in the form of decode circuitry to decode an instruction having fields for an opcode, a destination matrix operand identifier, and source memory information, and execution circuitry to execute the decoded instruction to load groups of strided data elements from memory into configured rows of the identified destination matrix operand to memory.

公开(公告)号：US12124846B2

公开(公告)日：2024-10-22

申请号：US18456699

申请日：2023-08-28

Applicant: INTEL CORPORATION

Inventor： Robert Valentine ,  Galina Ryvchin ,  Piotr Majcher ,  Mark J. Charney ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal ,  Milind B. Girkar ,  Zeev Sperber ,  Simon Rubanovich ,  Amit Gradstein

IPC: G06F9/30 ,  G06F7/544 ,  G06F9/38

CPC classification number: G06F9/30014 ,  G06F7/5443 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30105 ,  G06F9/3818

Abstract: Embodiments of systems, apparatuses, and methods for fused multiple add. In some embodiments, a decoder decodes a single instruction having an opcode, a destination field representing a destination operand, and fields for a first, second, and third packed data source operand, wherein packed data elements of the first and second packed data source operand are of a first, different size than a second size of packed data elements of the third packed data operand. Execution circuitry then executes the decoded single instruction to perform, for each packed data element position of the destination operand, a multiplication of a M N-sized packed data elements from the first and second packed data sources that correspond to a packed data element position of the third packed data source, add of results from these multiplications to a full-sized packed data element of a packed data element position of the third packed data source, and storage of the addition result in a packed data element position destination corresponding to the packed data element position of the third packed data source, wherein M is equal to the full-sized packed data element divided by N.