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    Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabricating thereof
    61.
    发明授权
    Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabricating thereof 失效
    具有窄宽度区域的电可编程熔丝结构被配置为增强电流拥挤及其制造方法

    公开(公告)号：US07531388B2

    公开(公告)日：2009-05-12

    申请号：US11876942

    申请日：2007-10-23

    申请人： Roger A. Booth, Jr. ,  William R. Tonti ,  Jack A. Mandelman

    发明人： Roger A. Booth, Jr. ,  William R. Tonti ,  Jack A. Mandelman

    IPC分类号： H01L21/82 ,  H01L21/44

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element. The first terminal portion has a maximum width greater than a maximum width of the fuse element, and the fuse includes a narrowed width region where the first terminal portion and fuse element interface. The narrowed width region extends at least partially into and includes part of the first terminal portion. The width of the first terminal portion in the narrowed region is less than the maximum width of the first terminal portion to enhance current crowding therein. In another implementation, the fuse element includes a restricted width region wherein width of the fuse element is less than the maximum width thereof to enhance current crowding therein, and length of the restricted width region is less than a total length of the fuse element.

    摘要翻译： 提出了电可编程熔丝结构及其制造方法，其中熔丝包括通过细长的熔丝元件互连的第一和第二端部。 第一端子部分具有大于熔丝元件的最大宽度的最大宽度，并且熔丝包括第一端子部分和熔丝元件接合的变窄的宽度区域。 狭窄宽度区域至少部分地延伸并包括第一端子部分的一部分。 变窄区域中的第一端子部分的宽度小于第一端子部分的最大宽度，以增强其中的电流拥挤。 在另一实施方式中，熔丝元件包括限制宽度区域，其中熔丝元件的宽度小于其最大宽度以增强其中的电流拥挤，并且受限宽度区域的长度小于熔丝元件的总长度。

    Pillar P-i-n semiconductor diodes
    62.
    发明授权
    Pillar P-i-n semiconductor diodes 失效
    支柱P-i-n半导体二极管

    公开(公告)号：US07525170B2

    公开(公告)日：2009-04-28

    申请号：US11538557

    申请日：2006-10-04

    申请人： Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  Kangguo Cheng

    发明人： Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  Kangguo Cheng

    IPC分类号： H01L31/058

    CPC分类号： H01L31/035281 ,  H01L27/1446 ,  H01L31/022408 ,  H01L31/022466 ,  H01L31/028 ,  H01L31/1804 ,  H01L31/1884 ,  Y02E10/547 ,  Y02P70/521

    摘要： An arrangement of pillar shaped p-i-n diodes having a high aspect ration are formed on a semiconductor substrate. Each device is formed by an intrinsic or lightly doped region (i-region) positioned between a P+ region and an N+ region at each end of the pillar. The arrangement of pillar p-i-n diodes is embedded in an optical transparent medium. For a given surface area, more light energy is absorbed by the pillar arrangement of p-i-n diodes than by conventional planar p-i-n diodes. The pillar p-i-n diodes are preferably configured in an array formation to enable photons reflected from one pillar p-i-n diode to be captured and absorbed by another p-i-n diode adjacent to the first one, thereby optimizing the efficiency of energy conversion.

    摘要翻译： 在半导体衬底上形成具有高纵横比的柱状p-i-n二极管的布置。 每个器件由位于柱的每个端部处的P +区域和N +区域之间的本征或轻掺杂区域（i区域）形成。 柱p-i-n二极管的布置被嵌入在光学透明介质中。 对于给定的表面积，p-i-n二极管的支柱排列比常规平面p-i-n二极管吸收更多的光能。 支柱p-i-n二极管优选地被配置成阵列形成，以使得从一个柱p-i-n二极管反射的光子被与第一个p-i-n二极管相邻的另一个p-i-n二极管捕获和吸收，从而优化了能量转换的效率。

    Trench memory cells with buried isolation collars, and methods of fabricating same
    64.
    发明授权
    Trench memory cells with buried isolation collars, and methods of fabricating same 有权
    具有埋置隔离套环的沟槽记忆单元及其制造方法

    公开(公告)号：US07427545B2

    公开(公告)日：2008-09-23

    申请号：US11164381

    申请日：2005-11-21

    申请人： Kangguo Cheng ,  Jack A. Mandelman

    发明人： Kangguo Cheng ,  Jack A. Mandelman

    IPC分类号： H01L21/76 ,  H01L21/44

    CPC分类号： H01L29/945 ,  H01L27/1087

    摘要： The present invention relates to semiconductor devices, preferably dynamic random access memory (DRAM) cells, each of which contains at least one trench capacitor with a buried isolation collar. The trench capacitor is located in a trench in a semiconductor substrate, and it comprises inner and outer electrodes and a dielectric layer. The buried isolation collar is recessed into a sidewall of the trench and has a substantially uniform thickness. Such a buried isolation collar is preferably formed by oxygen implantation before trench etching.

    摘要翻译： 本发明涉及半导体器件，优选动态随机存取存储器（DRAM）单元，每个单元包含至少一个具有埋入隔离环的沟槽电容器。 沟槽电容器位于半导体衬底中的沟槽中，并且其包括内电极和外电极以及电介质层。 埋入的隔离套环凹入沟槽的侧壁并且具有基本均匀的厚度。 这种埋置的隔离环优选通过在沟槽蚀刻之前的氧注入形成。

    Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabrication thereof
    65.
    发明授权
    Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabrication thereof 有权
    具有变宽的宽度区域的电可编程熔丝结构被配置为增强电流拥挤及其制造方法

    公开(公告)号：US07417300B2

    公开(公告)日：2008-08-26

    申请号：US11372386

    申请日：2006-03-09

    申请人： Roger A. Booth, Jr. ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Roger A. Booth, Jr. ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element. The first terminal portion has a maximum width greater than a maximum width of the fuse element, and the fuse includes a narrowed width region where the first terminal portion and fuse element interface. The narrowed width region extends at least partially into and includes part of the first terminal portion. The width of the first terminal portion in the narrowed region is less than the maximum width of the first terminal portion to enhance current crowding therein. In another implementation, the fuse element includes a restricted width region wherein width of the fuse element is less than the maximum width thereof to enhance current crowding therein, and length of the restricted width region is less than a total length of the fuse element.

    摘要翻译： 提出了电可编程熔丝结构及其制造方法，其中熔丝包括通过细长的熔丝元件互连的第一和第二端部。 第一端子部分具有大于熔丝元件的最大宽度的最大宽度，并且熔丝包括第一端子部分和熔丝元件接合的变窄的宽度区域。 狭窄宽度区域至少部分地延伸并包括第一端子部分的一部分。 变窄区域中的第一端子部分的宽度小于第一端子部分的最大宽度，以增强其中的电流拥挤。 在另一实施方式中，熔丝元件包括限制宽度区域，其中熔丝元件的宽度小于其最大宽度以增强其中的电流拥挤，并且受限宽度区域的长度小于熔丝元件的总长度。

    PATTERNED SILICON-ON-INSULATOR LAYERS AND METHODS FOR FORMING THE SAME
    66.
    发明申请
    PATTERNED SILICON-ON-INSULATOR LAYERS AND METHODS FOR FORMING THE SAME 有权
    图案的绝缘硅绝缘层及其形成方法

    公开(公告)号：US20080157261A1

    公开(公告)日：2008-07-03

    申请号：US12049258

    申请日：2008-03-14

    申请人： Roger Allen Booth, ,  Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Roger Allen Booth, ,  Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： H01L27/12

    CPC分类号： H01L21/76243

    摘要： In an aspect, a method is provided for forming a silicon-on-insulator (SOI) layer. The method includes the steps of (1) providing a silicon substrate; (2) selectively implanting the silicon substrate with oxygen using a low implant energy to form an ultra-thin patterned seed layer; and (3) employing the ultra-thin patterned seed layer to form a patterned SOI layer on the silicon substrate. Numerous other aspects are provided.

    摘要翻译： 在一方面，提供了一种用于形成绝缘体上硅（SOI）层的方法。 该方法包括以下步骤：（1）提供硅衬底; （2）使用低注入能量用氧选择性地注入硅衬底以形成超薄图案种子层; 和（3）使用超薄图案种子层在硅衬底上形成图案化SOI层。 提供了许多其他方面。

    Strained finFET CMOS device structures
    67.
    发明授权
    Strained finFET CMOS device structures 有权
    应变finFET CMOS器件结构

    公开(公告)号：US07388259B2

    公开(公告)日：2008-06-17

    申请号：US10536483

    申请日：2002-11-25

    申请人： Bruce B. Doris ,  Dureseti Chidambarrao ,  MeiKei Ieong ,  Jack A. Mandelman

    发明人： Bruce B. Doris ,  Dureseti Chidambarrao ,  MeiKei Ieong ,  Jack A. Mandelman

    IPC分类号： H01L29/94

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/7843 ,  H01L29/785

    摘要： A semiconductor device structure, includes a PMOS device 200 and an NMOS device 300 disposed on a substrate 1,2, the PMOS device including a compressive layer 6 stressing an active region of the PMOS device, the NMOS device including a tensile layer 9 stressing an active region of the NMOS device, wherein the compressive layer includes a first dielectric material, the tensile layer includes a second dielectric material, and the PMOS and NMOS devices are FinFET devices 200, 300.

    摘要翻译： 半导体器件结构包括PMOS器件200和设置在衬底1,2上的NMOS器件300，PMOS器件包括压迫PMOS器件的有源区的压缩层6，NMOS器件包括拉伸层9， 所述NMOS器件的有源区，其中所述压缩层包括第一介电材料，所述拉伸层包括第二介电材料，并且所述PMOS和NMOS器件为FinFET器件200,300。

    Programmable capacitors and methods of using the same
    68.
    发明授权
    Programmable capacitors and methods of using the same 有权
    可编程电容器及其使用方法

    公开(公告)号：US07358823B2

    公开(公告)日：2008-04-15

    申请号：US11353516

    申请日：2006-02-14

    申请人： Wagdi W. Abadeer ,  Anthony R. Bonaccio ,  Jack A. Mandelman ,  William R. Tonti ,  Sebastian T. Ventrone

    发明人： Wagdi W. Abadeer ,  Anthony R. Bonaccio ,  Jack A. Mandelman ,  William R. Tonti ,  Sebastian T. Ventrone

    IPC分类号： H03B5/12

    CPC分类号： H03L7/099 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03L7/095 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/06

    摘要： In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode; and (2) employing the transistor in a circuit. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供了一种调整半导体器件的电容的方法。 第一种方法包括以下步骤：（1）提供包括具有约3.9至约25的介电常数的介电材料的晶体管，其中该晶体管适于在第一模式下工作以提供电容，并进一步适于在 将晶体管的阈值电压从初始阈值电压改变到改变的阈值电压，使得当在第一模式中操作时，改变的阈值电压影响由晶体管提供的电容; 和（2）在电路中采用晶体管。 提供了许多其他方面。