公开(公告)号：US20160343694A1

公开(公告)日：2016-11-24

申请号：US15066241

申请日：2016-03-10

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  I-Hsuan PENG ,  Ching-Wen HSIAO

IPC: H01L25/16 ,  H01L21/78 ,  H01L25/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a semiconductor package. The semiconductor package includes a semiconductor die. A redistribution layer (RDL) structure is disposed on the semiconductor die and is electrically connected to the semiconductor die. An active or passive element is disposed between the semiconductor die and the RDL structure. A molding compound surrounds the semiconductor die and the active or passive element.

Abstract translation: 提供半导体封装组件。 半导体封装组件包括半导体封装。 半导体封装包括半导体管芯。 再分配层（RDL）结构设置在半导体管芯上并与半导体管芯电连接。 有源或无源元件设置在半导体管芯和RDL结构之间。 模制化合物围绕半导体管芯和有源或无源元件。

公开(公告)号：US20150348932A1

公开(公告)日：2015-12-03

申请号：US14825443

申请日：2015-08-13

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  Ching-Liou HUANG ,  Thomas Matthew GREGORICH

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/29 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer is formed such a portion of the solder resist layer and a portion of the first conductive trace collectively have a T-shaped cross section.

Abstract translation: 本发明提供一种半导体封装。 半导体封装包括衬底。 第一导电迹线设置在衬底上。 布置在基板上的第一导电迹线。 半导体管芯设置在第一导电迹线上。 形成阻焊层，阻焊层的一部分和第一导电性迹线的一部分共同具有T形截面。

公开(公告)号：US20150214192A1

公开(公告)日：2015-07-30

申请号：US14539180

申请日：2014-11-12

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/373 ,  H01L25/00 ,  H01L23/00

Abstract: A chip package structure and a method for forming a chip package are provided. The chip package structure includes a chip package over a printed circuit board and multiple conductive bumps between the chip package and the printed circuit board. The chip package structure also includes one or more thermal conductive elements between the chip package and the printed circuit board. The thermal conductive element has a thermal conductivity higher than a thermal conductivity of each of the conductive bumps.

Abstract translation: 提供了芯片封装结构和芯片封装形成方法。 芯片封装结构包括印刷电路板上的芯片封装和芯片封装与印刷电路板之间的多个导电凸块。 芯片封装结构还包括在芯片封装和印刷电路板之间的一个或多个导热元件。 导热元件的导热率高于每个导电凸块的导热率。

公开(公告)号：US20140091481A1

公开(公告)日：2014-04-03

申请号：US14103066

申请日：2013-12-11

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  Ching-Liou HUANG ,  Thomas Matthew GREGORICH

IPC: H01L23/00

CPC classification number: H01L24/29 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, an underfill material is provided that fills a gap between the substrate and the semiconductor die.

Abstract translation: 本发明提供一种半导体封装。 半导体封装包括衬底。 第一导电迹线设置在衬底上。 布置在基板上的第一导电迹线。 半导体管芯设置在第一导电迹线上。 还包括延伸穿过半导体管芯的边缘的阻焊层。 最后，提供填充衬底和半导体管芯之间的间隙的底部填充材料。