公开(公告)号：US4802221A

公开(公告)日：1989-01-31

申请号：US887492

申请日：1986-07-21

Applicant: Mahmoud K. Jibbe

Inventor： Mahmoud K. Jibbe

IPC: G10L11/00 ,  G10L11/02 ,  G10L11/04 ,  G10L11/06 ,  G10L19/00 ,  H03M7/46 ,  G10L5/00

CPC classification number: H03M7/46 ,  G10L19/00 ,  G10L25/00 ,  G10L25/78 ,  G10L25/90 ,  G10L25/93

Abstract: The system and method of the invention operates upon a serial bit stream of speech encoded data by reading the data in fixed length frames. Each frame is classified as to whether the frame represents voiced, unvoiced, or a silence condition. For a voiced frame, the pitches are detected. The bits of the voiced frame are then compared with the bits of prior received voiced frames, on a pitch basis, so as to detect repetition. When repetition is detected, the repetition count, the pitch period, and the one set of the repetitive pitch bits are stored ready for transmission. The compressed data is reconstructed by utilizing a decoder which interprets the stored information and causes reinsertion of the repetitions.

Abstract translation: 本发明的系统和方法通过以固定长度的帧读取数据来操作语音编码数据的串行比特流。 每个帧被分类为帧是表示浊音，清音还是静音状态。 对于有声框架，检测音高。 然后将有声帧的比特与先前接收的有声帧的比特基于音调进行比较，以便检测重复。 当检测到重复时，存储重复计数，音调周期和一组重复音调比特以准备传输。 通过利用解释所存储的信息并导致重新插入重复的解码器来重建压缩数据。

公开(公告)号：US08843808B2

公开(公告)日：2014-09-23

申请号：US13173184

申请日：2011-06-30

Applicant: Mahmoud K. Jibbe ,  Arunkumar Ragendran ,  Britto Rossario ,  Senthil Kannan ,  Padmanabhan Pandurangan

Inventor： Mahmoud K. Jibbe ,  Arunkumar Ragendran ,  Britto Rossario ,  Senthil Kannan ,  Padmanabhan Pandurangan

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10

CPC classification number: G06F11/0727 ,  G06F11/0772 ,  G06F11/1004 ,  G06F2211/1088

Abstract: An apparatus comprising an array controller and a frame buffer. The array controller may be configured to read/write data to/from a drive array in response to one or more input/output requests. The frame buffer may be implemented within the array controller and may be configured to perform (i) a first data integrity check to determine a first type of data error and (ii) a second data integrity check to determine a second type of data error. The frame buffer may log occurrences of the first type of error and the second type of error in a field transmitted with the data. The field may be used to determine a source of possible corruption of the data.

Abstract translation: 一种包括阵列控制器和帧缓冲器的装置。 阵列控制器可以被配置为响应于一个或多个输入/输出请求向/从驱动器阵列读取/写入数据。 帧缓冲器可以在阵列控制器内实现，并且可以被配置为执行（i）第一数据完整性检查以确定第一类型的数据错误，以及（ii）第二数据完整性检查以确定第二类型的数据错误。 帧缓冲器可以在与数据一起发送的字段中记录第一类型的错误和第二类型的错误的出现。 该字段可用于确定可能的数据损坏的来源。

公开(公告)号：US08677461B2

公开(公告)日：2014-03-18

申请号：US13091381

申请日：2011-04-21

Applicant: Mahmoud K. Jibbe ,  Chandan A. Marathe ,  Manjunath Balgatte Gangadharan ,  Natesh Somanna

Inventor： Mahmoud K. Jibbe ,  Chandan A. Marathe ,  Manjunath Balgatte Gangadharan ,  Natesh Somanna

IPC: H04L29/06

CPC classification number: H04L63/08 ,  G06F21/44 ,  G06F21/572 ,  G06F21/80 ,  G06F21/85 ,  G06F2221/2129 ,  H04L9/0894 ,  H04L9/16 ,  H04L63/108

Abstract: An apparatus comprising a controller circuit and an array. The controller circuit may be configured to read/write data in response to one or more input/output requests. The array may be configured to present/receive data to/from the controller circuit in response to the input/output requests. The data may be only transmitted to/from the array after a successful authentication between (i) a first code embedded within each of the input/output requests and (ii) a second code stored on a non-volatile memory within the controller circuit.

Abstract translation: 一种包括控制器电路和阵列的装置。 控制器电路可以被配置为响应于一个或多个输入/输出请求来读/写数据。 阵列可以被配置为响应于输入/输出请求向控制器电路呈现/接收数据。 在（i）嵌入在每个输入/输出请求中的第一代码和（ii）存储在控制器电路内的非易失性存储器上的第二代码之间的成功认证之后，数据可以仅被发送到数组或从阵列发送。

公开(公告)号：US08473645B2

公开(公告)日：2013-06-25

申请号：US13083864

申请日：2011-04-11

Applicant: Mahmoud K. Jibbe ,  Arunkumar Ragendran ,  Britto Rossario ,  Senthil Kannan

Inventor： Mahmoud K. Jibbe ,  Arunkumar Ragendran ,  Britto Rossario ,  Senthil Kannan

IPC: G06F13/00

CPC classification number: G06F3/0613 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/067 ,  Y02D10/154

Abstract: An apparatus comprising an interface circuit and a controller. The interface circuit may be configured to calculate a speed signal in response to data traffic measured over a network. The controller may be configured to present and receive data from an array in response to (a) the speed signal and (b) one or more input/output requests. The interface circuit may generate the speed signal in response to a plurality of predetermined factors. The controller may present and receive the data at one of a plurality of speeds in response to the speed signal.

Abstract translation: 一种包括接口电路和控制器的装置。 接口电路可以被配置为响应于通过网络测量的数据业务来计算速度信号。 控制器可以被配置为响应于（a）速度信号和（b）一个或多个输入/输出请求，从阵列呈现和接收数据。 接口电路可以响应于多个预定因素而产生速度信号。 控制器可以响应于速度信号以多个速度中的一个呈现和接收数据。

公开(公告)号：US20130007531A1

公开(公告)日：2013-01-03

申请号：US13173184

申请日：2011-06-30

Applicant: Mahmoud K. Jibbe ,  Arunkumar Ragendran ,  Britto Rossario ,  Senthil Kannan ,  Padmanabhan Pandurangan

Inventor： Mahmoud K. Jibbe ,  Arunkumar Ragendran ,  Britto Rossario ,  Senthil Kannan ,  Padmanabhan Pandurangan

IPC: G06F11/07

CPC classification number: G06F11/0727 ,  G06F11/0772 ,  G06F11/1004 ,  G06F2211/1088

Abstract: An apparatus comprising an array controller and a frame buffer. The array controller may be configured to read/write data to/from a drive array in response to one or more input/output requests. The frame buffer may be implemented within the array controller and may be configured to perform (i) a first data integrity check to determine a first type of data error and (ii) a second data integrity check to determine a second type of data error. The frame buffer may log occurrences of the first type of error and the second type of error in a field transmitted with the data. The field may be used to determine a source of possible corruption of the data.

Abstract translation: 一种包括阵列控制器和帧缓冲器的装置。 阵列控制器可以被配置为响应于一个或多个输入/输出请求向/从驱动器阵列读取/写入数据。 帧缓冲器可以在阵列控制器内实现，并且可以被配置为执行（i）第一数据完整性检查以确定第一类型的数据错误，以及（ii）第二数据完整性检查以确定第二类型的数据错误。 帧缓冲器可以在与数据一起发送的字段中记录第一类型的错误和第二类型的错误的出现。 该字段可用于确定可能的数据损坏的来源。

公开(公告)号：US20120317316A1

公开(公告)日：2012-12-13

申请号：US13158621

申请日：2011-06-13

Applicant: Madhukar Gunjan Chakhaiyar ,  Mahmoud K. Jibbe

Inventor： Madhukar Gunjan Chakhaiyar ,  Mahmoud K. Jibbe

IPC: G06F3/00

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0689

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of intermediate signals in response to a plurality of input/output requests. The second circuit may be configured to generate a plurality of processed input/output requests in response to the plurality of input/output requests. The processed input/output requests may be configured to be processed by a drive controller to access a drive array in accordance with a protocol used to process the input/output requests.

Abstract translation: 一种包括第一电路和第二电路的装置。 第一电路可以被配置为响应于多个输入/输出请求而产生多个中间信号。 第二电路可以被配置为响应于多个输入/输出请求而产生多个经处理的输入/输出请求。 经处理的输入/输出请求可被配置为由驱动器控制器处理，以根据用于处理输入/输出请求的协议访问驱动器阵列。

公开(公告)号：US20120265994A1

公开(公告)日：2012-10-18

申请号：US13085777

申请日：2011-04-13

Applicant: Mahmoud K. Jibbe ,  Senthil Kannan ,  Arunkumar Ragendran ,  Britto Rossario

Inventor： Mahmoud K. Jibbe ,  Senthil Kannan ,  Arunkumar Ragendran ,  Britto Rossario

IPC: H04L9/32

CPC classification number: H04L9/3234 ,  G06F21/44

Abstract: A method for establishing a secure connection between a first computer and a second computer, comprising the steps of (A) generating a signature authentication pair on the first computer, (B) receiving a plurality of authentication pairs that may or may not include the signature authentication pair, (C) detecting whether the signature authentication pair is received in the authentication pairs and (D) if the signature authentication pair is detected, creating a secure connection between the first computer and the second computer.

Abstract translation: 一种用于在第一计算机和第二计算机之间建立安全连接的方法，包括以下步骤：（A）在所述第一计算机上生成签名认证对，（B）接收可以包含或不包括签名的多个认证对 验证对，（C）检测认证对中是否接收到签名认证对，以及（D）如果检测到签名认证对，则在第一计算机和第二计算机之间建立安全连接。

公开(公告)号：US20120233604A1

公开(公告)日：2012-09-13

申请号：US13042697

申请日：2011-03-08

Applicant: Mahmoud K. Jibbe ,  Chandan A. Marathe

Inventor： Mahmoud K. Jibbe ,  Chandan A. Marathe

IPC: G06F9/44

CPC classification number: G06F8/654

Abstract: A method for updating software in a controller, comprising the steps of (A) comparing a current boot-set to a host boot-set to determine if a new boot-set is needed, (B) determining if one or more specifications of a new boot-set are met and (C) updating the controller to the new boot-set. An agent may control the controller during the updating to allow the controller to process data requests during the updating.

Abstract translation: 一种用于更新控制器中的软件的方法，包括以下步骤：（A）将当前引导集与主机引导集进行比较，以确定是否需要新引导集;（B）确定是否存在一个或多个规范 满足新引导集，（C）将控制器更新到新引导集。 代理可以在更新期间控制控制器，以允许控制器在更新期间处理数据请求。

公开(公告)号：US20120158652A1

公开(公告)日：2012-06-21

申请号：US12968297

申请日：2010-12-15

Applicant: Pavan Ps ,  Mahmoud K. Jibbe ,  Vivek Prakash ,  Madhukar Gunjan Chakhaiyar

Inventor： Pavan Ps ,  Mahmoud K. Jibbe ,  Vivek Prakash ,  Madhukar Gunjan Chakhaiyar

IPC: G06F17/30

CPC classification number: G06F11/1451 ,  G06F2201/82

Abstract: A system and method for ensuring consistency in RAID storage array metadata is disclosed. In one embodiment, the RAID storage array metadata residing in one or more drives is consolidated onto a metadata base volume that is in sync with the current RAID storage array metadata. Further, a point-in-time (PIT) image of the consolidated RAID storage array metadata in the metadata base volume, a system configuration (SC) file, and customer support data (CSD) are obtained. The PIT image, the SC file and CSD can be obtained based on a predetermined time interval and/or upon a change on the RAID storage array metadata. Furthermore, a delta change between two substantially sequentially obtained PIT images, SC files and CSD are determined. In addition, a consistency check (CC) is performed on the RAID storage array metadata based on the determined delta change.

Abstract translation: 公开了一种确保RAID存储阵列元数据一致性的系统和方法。 在一个实施例中，驻留在一个或多个驱动器中的RAID存储阵列元数据被整合到与当前RAID存储阵列元数据同步的元数据基本卷上。 此外，获得元数据基本卷中的整合RAID存储阵列元数据的时间点（PIT）图像，系统配置（SC）文件和客户支持数据（CSD）。 可以基于预定的时间间隔和/或在RAID存储阵列元数据的变化时获得PIT图像，SC文件和CSD。 此外，确定两个基本上顺序获得的PIT图像，SC文件和CSD之间的delta变化。 此外，基于所确定的增量变化，对RAID存储阵列元数据执行一致性检查（CC）。

公开(公告)号：US08181062B2

公开(公告)日：2012-05-15

申请号：US12732908

申请日：2010-03-26

Applicant: Pavan P S ,  Vivek Prakash ,  Mahmoud K. Jibbe

Inventor： Pavan P S ,  Vivek Prakash ,  Mahmoud K. Jibbe

IPC: G06F11/00

CPC classification number: G06F11/1076 ,  G06F2211/1014

Abstract: An apparatus comprising a logically contiguous group of at least two drives, a loop and a compression/decompression circuit. Each of the drives comprises (i) a first region configured to store compressed data of a previous drive and (ii) a second region configured to store uncompressed data of the drive. The loop may be connected to the next drive in the logically contiguous group. The compression/decompression circuit may be configured to compress and decompress the data stored on each of the drives.

Abstract translation: 一种装置，包括至少两个驱动器的逻辑上连续的组，循环和压缩/解压缩电路。 每个驱动器包括（i）被配置为存储先前驱动器的压缩数据的第一区域和（ii）被配置为存储驱动器的未压缩数据的第二区域。 循环可以连接到逻辑连续组中的下一个驱动器。 压缩/解压缩电路可以被配置为压缩和解压缩存储在每个驱动器上的数据。