Controller and driver communication for switching regulators
    61.
    发明授权
    Controller and driver communication for switching regulators 有权
    用于开关稳压器的控制器和驱动器通信

    公开(公告)号:US07782035B2

    公开(公告)日:2010-08-24

    申请号:US11935535

    申请日:2007-11-06

    IPC分类号: G05F1/40

    摘要: Pulse width modulation (PWM) controllers and output stage driver circuits and related methods of communicating switching regulator mode information. The controller includes circuitry that recognizes intervals when the load driven by the regulator is in a low power mode. Responsive to recognizing the low power mode, the controller generates a PWM mode signal having at least three (3) different levels including at least one intermediate level that is coupled to at least one driver. Based on the PWM mode signal, the regulator is switched into a power saving low power operational mode.

    摘要翻译: 脉冲宽度调制(PWM)控制器和输出级驱动电路以及相关的交流调节器模式信息的方法。 控制器包括当由调节器驱动的负载处于低功率模式时识别间隔的电路。 响应于识别低功率模式,控制器产生具有至少三(3)个不同电平的PWM模式信号,包括耦合到至少一个驱动器的至少一个中间电平。 基于PWM模式信号,调节器切换到省电低功耗工作模式。

    PHASE DOUBLER
    62.
    发明申请
    PHASE DOUBLER 有权
    相位双打

    公开(公告)号:US20100079175A1

    公开(公告)日:2010-04-01

    申请号:US12429238

    申请日:2009-04-24

    IPC分类号: H03K3/00 H03K5/04

    CPC分类号: H02M3/1584

    摘要: A phase doubler driver circuit includes a first input for receiving a input PWM drive signal. First control logic generates a first output PWM drive signal and a second output PWM drive signal responsive to the input PWM drive signal. In a first mode of operation, alternating pulses of the input PWM drive are output as the first output PWM drive signal and the second PWM output drive signal respectively. In a second mode of operation, the input PWM drive signal is provided as the first output PWM drive signal when a second phase current associated with the second output PWM drive signal exceeds a first phase current associated with the first output PWM drive signal and the input PWM drive signal is provided as the second output PWM drive signal when the phase current associated with the first output PWM signal exceed the phase current associated with the second output PWM signal. Second control logic adds an offset to a falling edge of the first output PWM drive signal responsive to a difference between a first current associated with the first phase current and an average current and for adding the offset to a falling edge of the second output PWM signal responsive to a difference between a second current associated with the second phase current and the average current, wherein the average current comprises the average of the first current and the second current. Drive circuitry generates drive signals responsive to each of the first output PWM drive signal and the second output PWM drive signal.

    摘要翻译: 倍增器驱动器电路包括用于接收输入PWM驱动信号的第一输入端。 第一控制逻辑产生响应于输入PWM驱动信号的第一输出PWM驱动信号和第二输出PWM驱动信号。 在第一操作模式中,输入PWM驱动的交替脉冲分别作为第一输出PWM驱动信号和第二PWM输出驱动信号输出。 在第二操作模式中,当与第二输出PWM驱动信号相关联的第二相电流超过与第一输出PWM驱动信号和输入相关联的第一相电流时,输入PWM驱动信号被提供为第一输出PWM驱动信号 当与第一输出PWM信号相关联的相电流超过与第二输出PWM信号相关的相电流时,提供PWM驱动信号作为第二输出PWM驱动信号。 第二控制逻辑响应于与第一相电流相关联的第一电流与平均电流之间的差异,并且将偏移加到第二输出PWM信号的下降沿,将补偿添加到第一输出PWM驱动信号的下降沿 响应于与第二相电流相关联的第二电流与平均电流之间的差异,其中平均电流包括第一电流和第二电流的平均值。 驱动电路根据第一输出PWM驱动信号和第二输出PWM驱动信号中的每一个产生驱动信号。

    GATE DRIVER TOPOLOGY FOR MAXIMUM LOAD EFFICIENCY
    63.
    发明申请
    GATE DRIVER TOPOLOGY FOR MAXIMUM LOAD EFFICIENCY 有权
    门极驱动器拓扑最大负载效率

    公开(公告)号:US20100007320A1

    公开(公告)日:2010-01-14

    申请号:US12563468

    申请日:2009-09-21

    IPC分类号: G05F1/10

    摘要: A circuit comprises a first input for receiving a supply voltage and a second input for receiving a sensed current signal from an output of a DC to DC converter. The circuit also includes an output voltage for providing an adjustable drive voltage to a drive circuit. The circuit additionally includes circuitry for adjusting the drive voltage responsive to supply voltage and the sensed current signal.

    摘要翻译: 电路包括用于接收电源电压的第一输入端和用于从DC至DC转换器的输出端接收感测的电流信号的第二输入端。 电路还包括用于向驱动电路提供可调驱动电压的输出电压。 电路还包括用于响应于电源电压和所感测的电流信号来调节驱动电压的电路。

    Gate driver topology for maximum load efficiency
    64.
    发明授权
    Gate driver topology for maximum load efficiency 有权
    门驱动器拓扑,以实现最大负载效率

    公开(公告)号:US07615940B2

    公开(公告)日:2009-11-10

    申请号:US11479675

    申请日:2006-06-30

    IPC分类号: G05F1/00

    摘要: A circuit comprises a first input for receiving a supply voltage and a second input for receiving a sensed current signal from an output of a DC to DC converter. The circuit also includes an output voltage for providing an adjustable drive voltage to a drive circuit. The circuit additionally includes circuitry for adjusting the drive voltage responsive to supply voltage and the sensed current signal.

    摘要翻译: 电路包括用于接收电源电压的第一输入端和用于从DC至DC转换器的输出端接收感测的电流信号的第二输入端。 电路还包括用于向驱动电路提供可调驱动电压的输出电压。 电路还包括用于响应于电源电压和所感测的电流信号来调节驱动电压的电路。

    PWM controller with dual-edge modulation using dual ramps
    65.
    发明授权
    PWM controller with dual-edge modulation using dual ramps 有权
    PWM控制器采用双路斜坡调制

    公开(公告)号:US07453250B2

    公开(公告)日:2008-11-18

    申请号:US11318081

    申请日:2005-12-23

    IPC分类号: G05F1/00

    摘要: A dual-edge modulation controller including first and second ramp circuits, first and second comparators, an error amplifier and pulse control logic. The first ramp circuit provides a leading-edge ramp synchronous with a clock. The error amplifier compares a feedback signal with a reference and provides a compensation signal. The first comparator compares the leading-edge ramp with the compensation signal and asserts a set signal. The second ramp circuit provides a trailing-edge ramp that begins ramping when the set signal is asserted. The second comparator compares the trailing-edge ramp with the compensation signal and asserts a reset signal. The pulse control logic asserts a PWM signal when the set signal is asserted and de-asserts the PWM signal when the reset signal is asserted. The controller may control multiple phases with current balancing. The slew rate of the ramps may be adjusted based on the number of PWM signal asserted.

    摘要翻译: 包括第一和第二斜坡电路,第一和第二比较器,误差放大器和脉冲控制逻辑的双边缘调制控制器。 第一个斜坡电路提供与时钟同步的前沿斜坡。 误差放大器将反馈信号与参考值进行比较,并提供补偿信号。 第一个比较器将前沿斜坡与补偿信号进行比较,并置位一个置位信号。 第二斜坡电路提供一个后沿斜坡,当设定信号被断言时开始斜坡。 第二个比较器将后沿斜坡与补偿信号进行比较,并确定复位信号。 当置位信号置位时,脉冲控制逻辑置位PWM信号,并在复位信号置位时取消置位PWM信号。 控制器可以通过电流平衡控制多个相。 斜坡的转换速率可以根据断言的PWM信号的数量进行调整。

    PULSE ADDING SCHEME FOR SMOOTH PHASE DROPPING AT LIGHT LOAD CONDITIONS FOR MULTIPHASE VOLTAGE REGULATORS
    66.
    发明申请
    PULSE ADDING SCHEME FOR SMOOTH PHASE DROPPING AT LIGHT LOAD CONDITIONS FOR MULTIPHASE VOLTAGE REGULATORS 有权
    用于多相电压调节器的轻负载条件下的平滑相位抖动的脉冲增加方案

    公开(公告)号:US20080272752A1

    公开(公告)日:2008-11-06

    申请号:US11954888

    申请日:2007-12-12

    IPC分类号: G05F1/00

    摘要: A multiphase regulator which includes an output node developing an output voltage, a feedback circuit determining error of the output voltage and providing a compensation signal indicative thereof, at least three phase circuits coupled in parallel to the output node, and an adaptive controller. Each phase circuit includes a modulation circuit and a switch circuit. Each modulation circuit receives the compensation signal and generates pulses on a corresponding one of the pulse modulation signals. Each switch circuit is coupled to the output node and is controlled by a corresponding pulse modulation signal. The adaptive controller is responsive to a load indication signal, such as indicating a low load condition, and drops operation of at least one of the phase circuits and adds at least one pulse to a pulse modulation signal of each remaining phase circuit.

    摘要翻译: 多相调节器,其包括产生输出电压的输出节点,确定输出电压的误差的反馈电路,并提供指示其的补偿信号,与输出节点并联耦合的至少三相电路以及自适应控制器。 每相电路包括调制电路和开关电路。 每个调制电路接收补偿信号并在对应的一个脉冲调制信号上产生脉冲。 每个开关电路耦合到输出节点并由对应的脉冲调制信号控制。 自适应控制器响应诸如指示低负载状况的负载指示信号,并且降低至少一个相位电路的操作,并且将至少一个脉冲添加到每个剩余相位电路的脉冲调制信号。

    ADAPTIVE PWM PULSE POSITIONING FOR FAST TRANSIENT RESPONSE
    67.
    发明申请
    ADAPTIVE PWM PULSE POSITIONING FOR FAST TRANSIENT RESPONSE 有权
    自适应PWM脉冲定位快速瞬态响应

    公开(公告)号:US20070109825A1

    公开(公告)日:2007-05-17

    申请号:US11383878

    申请日:2006-05-17

    IPC分类号: H02M1/12

    CPC分类号: H02M3/156 H02M3/33507

    摘要: An adaptive pulse positioning system for a voltage converter providing an output voltage, the system including a PWM generation circuit, a sensor, and a pulse positioning circuit. The PWM generation circuit generates a PWM signal with PWM pulses for controlling the output voltage of the voltage controller. The sensor senses an output load condition of the voltage converter and provides a load signal indicative thereof. The pulse positioning circuit adaptively positions the PWM pulses based on the load signal. A method of adaptively positioning PWM pulses that are used to control an output voltage of a voltage regulator including generating a series of PWM pulses based on a clock signal, sensing an output load condition, and adaptively shifting the series of PWM pulses based on the output load condition.

    摘要翻译: 一种用于提供输出电压的电压转换器的自适应脉冲定位系统,该系统包括PWM生成电路,传感器和脉冲定位电路。 PWM生成电路生成PWM信号,PWM脉冲用于控制电压控制器的输出电压。 传感器感测电压转换器的输出负载状态,并提供指示其的负载信号。 脉冲定位电路根据负载信号自适应地定位PWM脉冲。 一种自适应地定位用于控制电压调节器的输出电压的PWM脉冲的方法,包括基于时钟信号产生一系列PWM脉冲,感测输出负载条件,以及基于输出自适应地移位一系列PWM脉冲 负载条件。

    Compensation offset adjustment scheme for fast reference voltage transitioning
    68.
    发明申请
    Compensation offset adjustment scheme for fast reference voltage transitioning 有权
    用于快速参考电压转换的补偿偏移调整方案

    公开(公告)号:US20070108954A1

    公开(公告)日:2007-05-17

    申请号:US11395909

    申请日:2006-03-31

    IPC分类号: G05F1/00

    CPC分类号: H02M3/156

    摘要: A PWM control circuit for a voltage regulator including a compensation network, a ramp generator providing a ramp voltage, an offset adjust circuit and a comparator circuit. The compensation network senses the output voltage, receives a reference voltage, and outputs a compensation voltage. The offset adjust circuit adjusts a selected one of the ramp voltage and the compensation voltage based on the reference voltage. The comparator circuit compares the compensation voltage with the ramp voltage and provides a PWM signal for controlling the output voltage. The offset adjust circuit may generate an offset voltage based on the reference voltage and a gain G of the voltage regulator. The offset adjust circuit may subtract the offset voltage from either the ramp voltage or the compensation voltage to provide an adjusted voltage to the comparator circuit.

    摘要翻译: 一种用于包括补偿网络的电压调节器的PWM控制电路,提供斜坡电压的斜坡发生器,偏移调整电路和比较器电路。 补偿网络感测输出电压,接收参考电压,并输出补偿电压。 偏移调整电路根据参考电压调整斜坡电压和补偿电压中选择的一个。 比较器电路将补偿电压与斜坡电压进行比较,并提供用于控制输出电压的PWM信号。 偏移调整电路可以基于参考电压和电压调节器的增益G产生偏移电压。 偏移调整电路可以从斜坡电压或补偿电压中减去偏移电压,以向比较器电路提供经调整的电压。